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Preliminary Information
16K
X1240
2-Wire RTC
Real Time Clock/Calendar with EEPROM
FEATURES
• 2-Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1240 is a Real Time Clock with clock/calendar
circuits. The dual port clock register allows the clock to
operate, without loss of accuracy, even during read and
write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1240 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
16K
EEPROM
Array
©Xicor, Inc. 1994, 1995, 1996, 1997, 1998, 1999 Patents Pending
9900-3003.5 12/6/99 CM
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Characteristics subject to change without notice

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X1240
PIN CONFIGURATION
X1240
8 pin SOIC
X1 1
X2 2
NC 3
VSS 4
8
7
6
5
VCC
VBack
SCL
SDA
X1240
8 pin TSSOP
VBack
VCC
X1
1
2
3
8 SCL
7 SDA
6 VSS
X2 4 5 NC
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and
may be wire ORed with other open drain or open col-
lector outputs. The input buffer is always active (not
gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz 2-wire
interface speeds.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails.
X1, X2
The X1 and X2 pins are the input and output, respec-
tively, of an inverting amplifier that can be configured
for use as an on-chip oscillator. A 32.768kHz quartz
crystal is used. Recommeded crystals are Sieko VT-200
or Epson C-002RX. The crystal supplies a timebase
for a clock/oscillator. The internal clock can be driven
by an external signal on X1, with X2 left unconnected.
Figure 1. Recommended Crystal connection
18pF
43pF
10M
220K
X1
X2
POWER CONTROL OPERATION
The Power control circuit accepts a VCC and a VBACK
input. The power control circuit will switch to VBACK
when VCC < VBACK - 0.2V. It will switch back to VCC
when VCC exceeds VBACK.
Figure 2. Power Control
VBACK
VCC = VBACK -0.2V
VCC
Internal
Voltage
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external, 32.768KHz
quartz crystal to maintain an accurate internal repre-
sentation of the year, month, day, date, hour, minute,
and seconds. The RTC has leap-year correction and a
century byte. The clock will also correct for months hav-
ing fewer than 31 days and will have a bit that controls
24 hour or AM/PM format. When the X1240 powers up
after the loss of both VCC and VBACK, the clock will not
increment until at least one byte is written to the clock
register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change dur-
ing the course of a read operation. In this device, the
time is latched by the read command (falling edge of
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X1240
the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a seperate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the first “one second” clock cycle after
the stop bit. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any nonvolatile write sequences.
A single byte may be written to the RTC without affect-
ing the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
logically separated from the array and are only acces-
sible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address in
the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to
the Clock/Control Registers.”)
The CCR is divided into 3 sections. These are:
1. Control (2 bytes)
2. Real Time Clock (8 bytes)
3. Status (1 byte)
Sections 1) and 2) are nonvolatile and Section 3) is
volatile. Each register is read and written through buff-
ers. The non-volatile portion (or the counter portion of
the RTC) is updated only if RWEL is set and only after
a valid write operation and stop bit. A sequential read or
page write operation provides access to the contents
of only one section of the CCR per operation. Access
to another section requires a new operation. Contin-
ued reads or writes, once reaching the end of a sec-
tion, will wrap around to the start of the section. A read
or page write can begin at any address in the CCR.
Section 3) is a volatile register. It is not necessary to set
the RWEL bit prior to writing the status register. Section 3)
supports a single byte read or write only. Continued reads
or writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
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