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4K
X20C04
512 x 8 Bit
Nonvolatile Static RAM
FEATURES
• High reliability
—Endurance: 1,000,000 nonvolatile store
operations
—Retention: 100 years minimum
• Power-on recall
—EEPROM data automatically recalled into
SRAM upon power-up
• Lock out inadvertent store operations
• Low power CMOS
—Standby: 250µA
• Infinite EEPROM array recall, and RAM read and
write cycles
• Compatible with X2004
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (EEPROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology
to achieve low power and wide power-supply margin.
The X20C04 features the JEDEC approved pinout for
byte-wide memories, compatible with industry stan-
dard RAMs, ROMs, EPROMs, and EEPROMs.
The NOVRAM design allows data to be easily transferred
from RAM to EEPROM (store) and EEPROM to RAM
(recall). The store operation is completed in 5ms or less
and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
EEPROM, and a minimum 1,000,000 store operations
to the EEPROM. Data retention is specified to be
greater than 100 years.
BLOCK DIAGRAM
A3–A6
CE
OE
WE
NE
A0–A2
A7–A8
REV 1.0 6/21/00
Control
Logic
VCC Sense
EEPROM Array
Row
Select
512 x 8
SRAM
Array
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Column
Select
&
I/OS
I/O0–I/O7
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X20C04
PIN CONFIGURATION
Plastic CERDIP
NE 1
28 VCC
NC 2
27 WE
A7 3
26 NC
A6 4
25 A8
A5 5
24 NC
A4 6
23 NC
A3 7 X20C04 22 OE
A2 8
21 NC
A1 9
20 CE
A0 10
I/O0 11
19 I/O7
18 I/O6
I/O1 12
17 I/O5
I/O2 13
16 I/O4
VSS 14
15 I/O3
LCC
PLCC
4 3 2 1 32 31 30
A6 5
A5 6
29 A8
28 NC
A4 7
A3 8
A2 9
A1 10
X20C04
(Top View)
27 NC
26 NC
25 OE
24 NC
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
PIN NAMES
Symbol
A0–A8
I/O0–I/O7
WE
CE
OE
NE
VCC
VSS
NC
Description
Address inputs
Data input/output
Write enable
Chip enable
Output enable
Nonvolatile enable
+5V
Ground
No connect
PIN DESCRIPTIONS
Addresses (A0–A8)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read and recall operations.
Output Enable LOW disables a store operation regard-
less of the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the EEPROM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the EEPROM array (store and recall functions).
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a 2-
line control architecture to eliminate bus contention in a
system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
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X20C04
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the
X20C04.
Nonvolatile Operations
With NE LOW, recall operation is performed in the
same manner as RAM read operation. A recall opera-
tion causes the entire contents of the EEPROM to be
written into the RAM array. The time required for the
operation to complete is 5µs or less. A store operation
causes the entire contents of the RAM array to be
stored in the nonvolatile EEPROM. The time for the
operation to complete is 5ms or less.
Power-Up Recall
Upon power-up (VCC), the X20C04 performs an auto-
matic array recall. When VCC minimum is reached, the
recall is initiated, regardless of the state of CE, OE,
WE and NE.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvola-
tile memory and the RAM.
– VCC Sense—All functions are inhibited when VCC is
3.5V.
– A RAM write is required before a Store Cycle is
initiated.
– Write Inhibit—Holding either OE LOW, WE HIGH,
CE HIGH, or NE HIGH during power-up and power-
down will prevent an inadvertent store operation.
– Noise Protection—A combined WE, NE, OE and CE
pulse of less than 20ns will not initiate a Store Cycle.
– Noise Protection—A combined WE, NE, OE and CE
pulse of less than 20ns will not initiate a recall cycle.
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
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X20C04
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ....................–65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
respect to VSS......................................... –1V to +7V
D.C. output current ............................................. 10mA
Lead temperature (soldering, 10 seconds......... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Military
Min.
0°C
–40°C
–55°C
Max.
+70°C
+85°C
+125°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Supply Voltage
X20C04
Limits
5V ±10%
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Symbol
Parameter
lCC1 VCC current (active)
Min.
ICC2
ISB1
ISB2
ILI
ILO
VIL(1)
VIH(1)
VOL
VOH
VCC current during store
VCC standby current
(TTL input)
VCC standby current
(CMOS input)
Input leakage current
Output leakage current
Input LOW voltage
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
–1
2
2.4
Limits
Max.
100
10
10
250
10
10
0.8
VCC + 0.5
0.4
Unit
mA
mA
mA
µA
µA
µA
V
V
V
V
Test Conditions
NE = WE = VIH, CE = OE = VIL, Address inputs =
0.4V/2.4V levels@ f = 5MHz. All I/Os = Open
All inputs = VIH, All I/Os = open
CE = VIH, All other inputs = VIH, All I/Os = open
All inputs = VCC – 0.3V, All I/Os = open
VIN = VSS to VCC
VOUT = VSS to VCC, CE = VIH
IOL = 2.1mA
IOH = –400µA
POWER-UP TIMING
Symbol
tPUR(2)
tPUW(2)
Parameter
Power-up to RAM operation
Power-up to nonvolatile operation
Max.
100
5
Unit
µs
ms
CAPACITANCE TA = +25°C, F = 1MHz, VCC = 5V
Symbol
CI/O(2)
CIN(2)
Test
Input/output capacitance
Input capacitance
Max.
10
6
Unit
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
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X20C04
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Store cycles
Data retention
Min.
100,000
1,000,000
100
MODE SELECTION
CE WE NE
HXX
L HH
L LH
L LH
LHL
LLL
L HH
LLL
LHL
OE
X
L
H
H
L
H
H
L
H
Mode
Not selected
Read RAM
Write “1” RAM
Write “0” RAM
Array recall
Nonvolatile storing
Output disabled
Not allowed
No operation
Unit
Data changes per bit
Store cycles
Years
I/O
Output high Z
Output data
Input data high
Input data low
Output high Z
Output high Z
Output high Z
Output high Z
Output high Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
EQUIVALENT A.C. LOAD CIRCUIT
5V
Output
1.92K
1.37K
100pF
A.C. CONDITIONS OF TEST
Input pulse levels
Input rise and fall times
Input and output timing levels
0V to 3V
10ns
1.5V
REV 1.0 6/21/00
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Characteristics subject to change without notice. 5 of 15