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IA63484
Advanced CRT Controller
Preliminary Data Sheet
FEATURES
innovASIC
High-speed graphics
- Drawing rate: 200 ns/pixel max (color drawing)
- Commands: 38 commands including 23 graphic drawing commands:
Dot, Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint, Copy, etc.
- Colors: 16 bits/word: 1,2,4,8,16 bits/pix el (5 types) monochrome to 64k colors max
- Pattern RAM: 32 bytes
- Converts logical X-Y coordinate to physical address
- Color operation and conditional drawing
- Drawing area control for hardware clipping and hitting
Large frame-memory space
- Maximum 2 Mbytes graphic memory and 128 kbytes character memory separate from
MPU memory.
- Maximum Resolution: 4096 x 4096 pixels (1 bit/pixel mode)
CRT display control
- Split Screens: three displays and one window
- Zoom: 1 to 16 times
- Scroll: vertical and horizontal
Interleaved access mode for flashless display and superimposition
External synchronization between ARTCs or between ACRTC and external device (TV system
or other controller.
DMA interface
Two programmable cursors
Three Scan modes
- Non-interlaced
- Interlace sync
- Interlace sync and video
Interrupt request to MPU
256 characters/line 32 raster/ line, 4096 rasters/screen
Maximum clock frequency: 20MHz
CMOS, single +5V power supply
The IA63484 is a "plug-and-play" drop-in replacement for the original Hitachi© HD63484. This
replacement IC has been developed using innovASIC’s MILESTM, or Managed IC Lifetime
Extension System, cloning technology. This technology produces replacement ICs far more complex
than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the
design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies
the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA63484 including functional and
I/O descriptions, electrical characteristics, and applicable timing.
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
Page 1 of 32
www.innovasic.com
Customer Support:
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IA63484
Advanced CRT Controller
68 Pin Package: PLCC PINOUT
Pin Arrangement:
Preliminary Data Sheet
dack_n
dtack_n(T)
irq(O,D)
hsync_n
vsync_n
Vcc
exsync_n
Vss
Vss
d0(T)
d1(T)
d2(T)
d3(T)
d4(T)
d5(T)
d6(T)
d7(T)
9
27
1 68
IA63484
O,D: Open Drain
T: Three State
60
chr
mrd
draw_n
as_n
mcyc
Vss
Vss
clk_2
Vcc
mad5(T)
mad6(T)
mad7(T)
mad8(T)
mad9(T)
mad10(T)
44
mad11(T)
mad12(T)
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
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IA63484
Advanced CRT Controller
BLOCK DIAGRAM
Preliminary Data Sheet
Figure 1: System Block Diagram
Figure 2 illustrates the IA63484 system environment. The following paragraphs will further describe
the system block diagram and design in more detail.
MPU
(8/16b)
SYSTEM
MEMORY
DMAC
res_n
irq_n
d[15:0]
dtack_n
cs_n
ma[19:16]
as_n
mrd
L
rs
rw_n
dreq_n
dack_n
done_n
clk_2
Vss
Vcc
ACRTC
disp2_n
disp1_n
cud2_n
cud1_n
lpstb
exsync_n
vsync_n
hsync_n
mad[15:0]
FRAME
BUFFER
2MB, MAX
DOT SHIFTER
CRT
VIDEO
SIGNAL
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
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IA63484
Advanced CRT Controller
Preliminary Data Sheet
I/O SIGNAL DESCRIPTION:
The diagram below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
I/O Characteristics:
Signal Name
res_n
I/O
I
d[15,0]
rw_n
cs_n
rs
dtack_n
I/O
I
I
I
O
irq_n
dreq_n
dack
done_n
clk_2
O
I
I/O
I
I/O
mad[15,0]
as_n
O
O
MA16/R 0-*
MA1 9/ R A3
RA4
chr
mcyc
mrd
draw_n
disp1, disp2
O
O
O
O
O
O
O
cud1, cud2
vsync_n
hsync_n
exsync_n
lpstb
O
I/O
I
Group
MPU
Interface
DMAC
Interface
CRT
Interface
Description
ACRTC reset:
Data bus (three state): are the bidirectional data bus to the host mpu or dmac. D 0 -D
are used in 8-bit data bus mode.
Read/write strobe: controls the direction of host/ACRTC transformers.
Chip Select: enables transfers between the host and the ACRTC.
Register Select: selects the ACRTC register to be accessed. It is usually connected to
the least significant bit of the host address bus.
Data transfer acknowledge (three state): output provides asynchronous bus cycle
timing. It is compatible with the HD68000 mpu dtack output.
Interrupt request (open drain): output generates interrupt service requests to the
host MPU.
DMA request: recieves DMA acknowledge timing from the host DMAC.
DMA acknoledge:
DMA done: terminates DMA transfer. It is compatible with the HD68450 DMAC
DONE signal.
ARTC clock: is the baasic operating clock, twice the frequency of the dot clock.
Multiplexed frame buffer address/data bus: are the multiplexed frame buffer
address/data bus.
Address strobe: output demultiplexes the address/data bus.
Higer-order address bits/character screen rastar address:MA16/R0- MA19/RA3 are
the upper bits of the graphics screen ddress multiplexed with th lower bits of the
character screen raster address.
Higer-order character screen rastar address bit: is the high bit of the character screen
raster address (up to 32 rasters.)
Graphic or character screen access: output indicates whether a graphic or character
screen is being accessed.
Frame buffer memory acess timing signal: is the frame buffer access timing output,
1/2 the frequency of clk_2.
Frame buffer memory read: output controls the frame buffer data bus direction.
Draw/refresh signal: output differentiates between drawing and CRT displayrefresh
cycles.
Display enable: programmable display enable outputs can enable, disable, and blanck
logical screens.
Coursor Display: outputs provides cursor timing programmed by ACRTC parameters
such as cursor definition, cursor mode, cursor address, etc.
CRT vertical sync pulse: outputs the crt vertical synchronization pulse.
CRT horizontal sync pulse: outputs the crt horizontal synchronization pulse.
External sync:allows synchronization between multiple ACRTSs and other videro
signal generators.
Lightpen strobe: is the lightpen input
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
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IA63484
Advanced CRT Controller
Figure 2: IA63484 Block Diagram
res_n
Preliminary Data Sheet
dreq_n
dack_n
done_n
irq_n
DMA
Control
Unit
Interrupt
Control
Unit
Register
Address
Data
Drawing
Processor
20
16
draw_adrs[19:0]
draw_data[15:0]
draw_en
write
16
d[15:0]
cs_n
rs_n
rw_n
dtack_n
MPU
Interface
23 25
V cc V SS
disp_adrs[19:0]
Display
Processor
20
15
raster_adrs[4:0]
chr_int
ccud
lpstb
2
Timing
Processor 2
gcud[1:0]
hsync
vsync
exsync
disp[1:0]
m_cyc
as
clk2
16
4
CRT
Interface
2
2
draw_n
mrd
mad[15:0]
ma19_16_ra[3:0]
ra4
chr
lpstb
cud1_n, cud2_n
hsync_n
vsync_n
exsync_n
disp1_n, disp2_n
mcyc
as_n
clk_2
IA63484 System Description:
Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host
MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can
quickly saturate the shared bus.
The IA63484 uses separate host MPU and frame buffer interfaces. This allows the IA63484 full access to the
frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the
IA63484. A related benefit is that a large frame buffer (2 MB for each IA63484) can be used, even if the host
MPU has a smaller address space or segment size restriction.
The IA63484 can use an external Direct Memory Access Controller (DMAC) to increase system throughput
when many commands, parameters and data must be transferred to the IA63484. Advanced DMAC features
such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.
More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the
interface to the IA63484 can be handled under MPU software control.
While both IA63484 bus interfaces (host MPU and frame buffer) are 16 bits wide, the IA63484 also offers an
8 bit MPU mode for easy connection to popular 8 bit busses.
Copyright © 2003
innov ASIC
The End of Obsolescence
ENG 21101041201
Page 5 of 32
www.innovasic.com
Customer Support:
1−888−824−4184