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MK1422
OPL3/4+Codec Portable Clock Source
Description
The MK1422 is the ideal way to generate clocks
for sound in portable computers. It provides clocks
for Analog Devices’ or Crystal Semiconductor’s
stereo codecs, and Yamaha’s OPL3L, OPL3LS,
and OPL4. The MK1422 uses either a
14.318 MHz crystal, or a 14.318 MHz bus clock
input to synthesize the clocks required to drive the
codec, and the 33.868 MHz required for the FM
or wavetable music synthesizer. It includes a power
down pin to save power without using a FET. In an
8 pin SOIC, the MK1422 can save component
count, board space, and cost over surface mount
crystals, and increase reliability by eliminating
three mechanical devices from the board.
MicroClock offers many other parts with stereo
codec support. MicroClock invented sound clocks,
and has the widest product offering and greatest
production experience on these devices. The
MK1422 is pin compatible with MicroClock’s
popular MK1420 when the 14.318MHz clock
output is not used. See the MK14223 for 3.3V.
Block Diagram
VDD GND
Features
• Packaged in 8 pin SOIC
• Input crystal or clock frequency of 14.318 MHz
• Output clock frequencies of 16.934 MHz,
24.576 MHz, and 33.868 MHz
• 25mA drive capability at TTL levels
• Advanced, low power CMOS process
• Low jitter ensures full 16 bit S/N ratio
• Insensitive to input clock duty cycle
• Power down for portable computers
AC Coupling/Portable Applications
For applications in portable computers, see the
MK14223, which is specified to operate at 3.3V. It
is possible to drive the MK1422 with a 3.3V,
14.318MHz clock by a.c. coupling using a 0.01µF
capacitor connected in series to the X1 pin. But the
operating VDD on pin 2 must be 5V±10%. This
technique is also effective if the input clock doesn’t
meet the VIH and VIL specifications on page 3.
Additional Clocks or Features
If more than these three output clocks or features
such as output enable are needed, MicroClock can
provide a quick turn modification for your custom
requirements.
All Chip
Power Down
14.318 MHz
crystal or clock
X1/ICLK
X2
Crystal
Oscillator
Clock Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
16.934 MHz
24.576 MHz
33.868 MHz
MDS 1422 B
1
Revision 080698
Printed 11/15/00
Integrated Circuit Systems•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com

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Pin Assignment
X1/ICLK
VDD
GND
16.9M
1
2
3
4
MK1422
OPL3/4+Codec Portable Clock Source
Suggested Layout
14.318 MHz in
Pin 1 8
8 X2
7 PD
V
0.1µF
6 33.9M
5 24.6M
G
27
36
45
PD
33.9MHz
out
33(optional)
33(optional)
33(optional)
Pin Descriptions
16.9MHz out 24.6MHz out
Number
1
2
3
4
5
6
7
8
Name
X1/ICLK
VDD
GND
16.9M
24.6M
33.9M
PD
X2
Type
I
P
P
O
O
O
I
O
Description
Crystal Connection. Connect to a 14.318 MHz crystal or clock.
Connect to +5V.
Connect to ground.
16.9344 MHz clock output for stereo codec.
24.576 MHz clock output for stereo codec.
33.868 MHz clock output for OPL4.
Power Down. Shuts off entire chip when low. All clock outputs stop low.
Crystal Connection to a 14.318 MHz crystal, or leave unconnected for clock input.
Key: I = Input, O = output, P = power supply connection
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
22pF load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel
resonant 14.318 MHz, 16pF load, crystal is recommended. Load capacitor values near these are acceptable,
as is a series resonant crystal, but either will result in frequencies which are further off of the target
frequency. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of 0.1µF
should be connected between VDD and GND, and 33terminating resistors may be used on the clock
outputs.
MDS 1422 B
2
Revision 080698
Printed 11/15/00
Integrated Circuit Systems•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com

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MK1422
OPL3/4+Codec Portable Clock Source
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
Clock Outputs
Referenced to GND
Ambient Operating Temperature
Soldering Temperature
Max of 20 seconds
Storage temperature
DC CHARACTERISTICS
Operating Voltage, VDD
Input High Voltage, VIH, ICLK
Input Low Voltage, VIL, ICLK
Input High Voltage, VIH, PD
Input Low Voltage, VIL, PD
Output High Voltage, VOH
IOH=-25mA
Output Low Voltage, VOL
IOL=25mA
Output High Voltage, VOH
IOH=-4mA
Output Low Voltage, VOL
IOL=4mA
Operating Supply Current, IDD
No Load
Power Down Operating Current, IDDPD
No Load
Input Capacitance
Actual Mean Frequency versus Target
AC CHARACTERISTICS
Outputs
Input Clock Frequency
Input Clock Duty Cycle, 14.318MHz
Time above VDD/2
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle, 24.576MHz
Time above 1.5 V
Output Clock Duty Cycle, 16.9344 MHz
Time above 1.5 V
Output Clock Duty Cycle, 33.868MHz
Time above 1.5 V
Absolute Clock Period Jitter
Pins 4, 5, 6 only
One Sigma Clock Period Jitter
Pins 4, 5, 6 only
Minimum Typical Maximum
7
-0.5 VDD+.5V
-0.5 VDD+.5V
0 70
260
-65 150
4.5
VDD/2 + 1
2
2.4
VDD-0.4
VDD/2
VDD/2
18
20
7
5.5
VDD/2 - 1
0.8
0.4
0.4
±0.2
14.31818
20 80
1.5
1.5
40 50 60
45 50 55
45 50 55
-400 200
400
60
Units
V
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
V
mA
µA
pF
%
MHz
%
ns
ns
%
%
%
ps
ps
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Typical values are at 25°C.
MDS 1422 B
3
Revision 080698
Printed 11/15/00
Integrated Circuit Systems•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com