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K4M513233E - M(E)C/L/F
Mobile-SDRAM
4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 2Chips DDP 90Balls FBGA with 0.8mm ball pitch
( -MXXX : Leaded, -EXXX : Lead Free).
GENERAL DESCRIPTION
The K4M513233E is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
K4M513233E-M(E)C/L/F75
133MHz(CL=3)
K4M513233E-M(E)C/L/F1H
105MHz(CL=2)
K4M513233E-M(E)C/L/F1L
105MHz(CL=3)*1
- M(E)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)
Interface
LVCMOS
Package
90 FBGA
Leaded (Lead Free)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other
products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or
notebook computers, cell phones, televisions or visual monitors)
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." .
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
February 2004

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K4M513233E - M(E)C/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile-SDRAM
Bank Select
CLK
ADD
Data Input Register
4M x 32
4M x 32
4M x 32
4M x 32
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
CLK CKE
CS
RAS
CAS
WE DQM
LWE
LDQM
DQi
LDQM
February 2004

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K4M513233E - M(E)C/L/F
Mobile-SDRAM
Package Dimension and Pin Configuration
< Bottom View*1 >
E1
987654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
E
E/2
< Top View*2 >
90Ball(6x15) FBGA
123789
A DQ26 DQ24 VSS VDD DQ23 DQ21
B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
G A4 A5 A6
A2 DQM2 VDD
A10 A0
A1
H A7
A8 A12 NC BA1 A11
J CLK CKE A9 BA0 CS RAS
K DQM1 NC
NC CAS WE DQM0
L VDDQ DQ8 VSS
VDD DQ7 VSSQ
M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 VSS VDD DQ0 DQ2
Pin Name
Pin Function
CLK System Clock
Substrate(2Layer)
bz
A
A1
CS
CKE
A0 ~ A12
BA0 ~ BA1
Chip Select
Clock Enable
Address
Bank Select Address
< Top View*2 >
#A1 Ball Origin Indicator
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
DQM0 ~ DQM3
Data Input/Output Mask
DQ0 ~ 31
Data Input/Output
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
[Unit:mm]
Symbol
A
A1
E
E1
D
D1
e
b
z
Min
-
0.30
-
-
-
-
-
0.40
-
Typ
1.30
0.35
11.00
6.40
13.00
11.20
0.80
0.45
-
Max
1.40
0.40
-
-
-
-
-
0.50
0.10
February 2004

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K4M513233E - M(E)C/L/F
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 1.0
Short circuit current
IOS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
50
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70°C)
Parameter
Symbol
Min
Typ
Max
Supply voltage
VDD 2.7 3.0 3.6
VDDQ
2.7
3.0
3.6
Input logic high voltage
VIH 2.2 3.0 VDDQ + 0.3
Input logic low voltage
VIL -0.3 0 0.5
Output logic high voltage
VOH
2.4
-
-
Output logic low voltage
VOL -
- 0.4
Input leakage current
ILI -10 - 10
NOTES :
1. VIH (max) = 5.3V AC.The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V VOUT VDDQ.
Unit
V
V
V
V
V
V
uA
Note
1
2
IOH = -2mA
IOL = 2mA
3
CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Max
Clock
CCLK 3.0 12.0
RAS, CAS, WE, CS, CKE
CIN 3.0 12.0
DQM
CIN 1.5 6.0
Address
CADD
3.0
12.0
DQ0 ~ DQ31
COUT
3.0
6.5
Unit
pF
pF
pF
pF
pF
Note
February 2004

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K4M513233E - M(E)C/L/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70°C)
Parameter
Symbol
Test Condition
Version
-75 -1H -1L
Unit Note
Operating Current
(One Bank Active)
Burst length = 1
ICC1 tRC tRC(min)
IO = 0 mA
170 160 150 mA 1
Precharge Standby Current in ICC2P CKE VIL(max), tCC = 10ns
power-down mode
ICC2PS CKE & CLK VIL(max), tCC =
Precharge Standby Current
in non power-down mode
ICC2N
CKE VIH(min), CS VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
1.5
1.5
20
10
mA
mA
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P CKE VIL(max), tCC = 10ns
ICC3PS CKE & CLK VIL(max), tCC =
ICC3N
CKE VIH(min), CS VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
8
8
45
40
mA
mA
mA
Operating Current
(Burst Mode)
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
230 210 210 mA 1
Refresh Current
ICC5 tRC tRC(min)
-C
-L
Self Refresh Current
ICC6 CKE 0.2V
Internal TCSR
Full Array
-F
1/2 of Full Array
1/4 of Full Array
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported(In commercial Temp : Max 40°C/Max 70°C)
4. K4M513233E-M(E)C**
5. K4M513233E-M(E)L**
6. K4M513233E-M(E)F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
350 330 300
1800
1500
Max 40 Max 70
850 1300
600 900
500 700
mA
uA
°C
uA
2
4
5
3
6
February 2004