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1997-1/21
MITSUBISHI LSIs
M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,
-70VLL,-10VLL,-12VLL,-15VLL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M51008BFP,VP,RV,KV,KR are a 1048576-bit CMOS
static RAM organized as 131072 word by 8-bit which are
fabricated using high-performance triple polysilicon CMOS
technology. The use of resistive load NMOS cells and CMOS
periphery result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin
small outline package which is a high reliability and high density
surface mount device(SMD).Two types of devices are available.
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy
to design a printed circuit board.
FEATURES
Type name
M5M51008BFP,VP,RV,KV,KR-70VL
M5M51008BFP,VP,RV,KV,KR-10VL
M5M51008BFP,VP,RV,KV,KR-12VL
M5M51008BFP,VP,RV,KV,KR-15VL
M5M51008BFP,VP,RV,KV,KR-70VLL
M5M51008BFP,VP,RV,KV,KR-10VLL
M5M51008BFP,VP,RV,KV,KR-12VLL
M5M51008BFP,VP,RV,KV,KR-15VLL
Access
time
(max)
VCC
Power supply current
Active
(1MHz)
(max)
stand-by
(max)
70ns 3.3±0.3V
100ns
10mA
60µA
120ns 3.0±0.3V 10mA
150ns
55µA
70ns 3.3±0.3V 10mA
100ns
12µA
120ns 3.0±0.3V 10mA 11µA
150ns
Low stand-by current 0.3µA (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51008BFP ············ 32pin 525mil SOP
M5M51008BVP,RV ············ 32pin 8 X 20 mm2 TSOP
M5M51008BKV,KR ············ 32pin 8 X 13.4 mm2 TSOP
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
GND 16
32 VCC
31
A15
ADDRESS
INPUT
30
S2
CHIP SELECT
INPUT
W29 WRITE CONTROL
INPUT
28 A13
27 A8
26 A9
ADDRESS
INPUTS
25 A11
24
OE OUTPUT ENABLE
INPUT
23
A10
ADDRESS
INPUT
22
S1
CHIP SELECT
INPUT
21 DQ8
20 DQ7
19 DQ6
18 DQ5
DATA
INPUTS/
OUTPUTS
17 DQ4
Outline 32P2M-A
A11 1
A9 2
A8 3
A13 4
W5
S2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
M5M51008BVP,KV
32 OE
31 A10
30 S1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
APPLICATION
Small capacity memory units
Outline 32P3H-E(VP), 32P3K-B(KV)
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
NC 9
VCC 8
A15 7
S2 6
W5
A13 4
A8 3
A9 2
A11 1
M5M51008BRV,KR
17 A3
18 A2
19 A1
20 A0
21 DQ1
22 DQ2
23 DQ3
24 GND
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
30 S1
31 A10
32 OE
Outline 32P3H-F(RV), 32P3K-C(KR)
NC : NO CONNECTION
1 MITSUBISHI
ELECTRIC

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1997-1/21
MITSUBISHI LSIs
M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,
-70VLL,-10VLL,-12VLL,-15VLL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008B series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or
S2,whichever occurs first,requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the data
bus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
When setting S1 at a high level or S2 at a low level, the chip are
in a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the
memory data can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation in
the non-selected mode.
FUNCTION TABLE
S1 S2
XL
HX
LH
LH
LH
W OE Mode
DQ
ICC
X X Non selection High-impedance Stand-by
X X Non selection High-impedance Stand-by
LX
Write
Din
Active
HL
Read
Dout
Active
HH
High-impedance Active
BLOCK DIAGRAM
A4 8
A5 7
A6 6
A7 5
A12 4
A14 3
A16 2
A15 31
A13 28
A8 27
*
16
15
14
13
12
11
10
7
4
3
ADDRESS
INPUTS
A0 12
A2 10
A3 9
A10 23
20
18
17
31
A1 11
A11 25
A9 26
19
1
2
131072 WORDS
X 8 BITS
(1024 ROWS
X128 COLUMNS
X 8BLOCKS)
CLOCK
GENERATOR
* Pin numbers inside dotted line show those of TSOP
2
MITSUBISHI
ELECTRIC
*
21
22
23
25
26
27
28
29
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
DATA
INPUTS/
OUTPUTS
20 DQ7
21 DQ8
WRITE
5 29 W CONTROL
INPUT
30 22 S1 CHIP
6
30 S2
SELECT
INPUTS
OUTPUT
32 24 OE ENABLE
INPUT
8 32 VCC
24
16
GND
(0V)

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1997-1/21
MITSUBISHI LSIs
M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,
-70VLL,-10VLL,-12VLL,-15VLL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO Output voltage
Pd Power dissipation
Topr Operating temperature
Tstg Storage temperature
* –3.0V in case of AC ( Pulse width 30ns )
Conditions
With respect to GND
Ta=25°C
Ratings
– 0.3*~4.6
– 0.3*~Vcc + 0.3
(Max 4.6)
0~Vcc
700
0~70
– 65~150
Unit
V
V
V
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
-70VL, -70VLL
-10VL, -10VLL
-12VL, -12VLL
-15VL, -15VLL
VCC=3.3±0.3V
Min Typ Max
VCC=3.0±0.3V
Min Typ Max
VIH High-level input voltage
2.0
Vcc
+0.3V
2.0
Vcc
+0.3V
VIL
VOH1
Low-level input voltage
High-level output voltage 1 IOH= 0.5mA
0.3
0.6 0.3
0.6
2.4 2.4
VOH2
High-level output voltage 2 IOH= 0.05mA
Vcc
-0.5V
Vcc
-0.5V
VOL Low-level output voltage IOL=2mA
II Input current
VI=0~Vcc
IO
Output current in off-state
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
ICC1
Active supply current
(Min cycle )
ICC2
Active supply current
(1MHz)
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
ICC3 Stand-by current
1) S2 0.2V
2) S1 VCC–0.2V,
S2 VCC–0.2V
other inputs=0~VCC
-L
-LL
0.4
±1
±1
20 35
3 10
60
12
0.4
±1
±1
15 30
3 10
55
11
ICC4 Stand-by current
* –3.0V in case of AC ( Pulse width 30ns )
S1=VIH or S2=VIL,
other inputs=0~VCC
0.33
0.33
Unit
V
V
V
V
V
µA
µA
mA
µA
mA
CAPACITANCE (Ta=0~70°C, unless otherwise noted)
Symbol
Parameter
CI Input capacitance
CO Output capacitance
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 3V, Ta = 25°C
Test conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Limits
Min Typ Max
6
8
Unit
pF
pF
3 MITSUBISHI
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1997-1/21
MITSUBISHI LSIs
M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,
-70VLL,-10VLL,-12VLL,-15VLL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
VCC ................................. 3.3±0.3V(-70VL,-70VLL,-10VL,-10VLL)
3.0±0.3V(-12VL,-12VLL,-15VL,-15VLL)
Input pulse level ............. VIH=2.2V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ...............VOH=VOL=1.5V
Output loads ................... Fig.1,CL=100pF (-15VL,-15VLL,)
CL=30pF (-70VL,-10VL,12VL,-70VLL,-10VLL,12VLL)
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
-70VL,VLL
Min Max
70
70
70
70
35
25
25
25
10
10
5
10
Limits
-10VL,VLL
-12VL,VLL
Min Max Min Max
100 120
100 120
100 120
100 120
50 60
35 40
35 40
35
10
40
10
10 10
55
10 10
-15VL,VLL
Min Max
150
150
150
150
75
50
50
50
10
10
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
-70VL,VLL
Min Max
70
55
0
65
65
65
30
0
0
25
25
5
5
Limits
-10VL,VLL
Min Max
-12VL,VLL
Min Max
100 120
75 85
00
85 100
85 100
85 100
40 45
00
00
35 40
35 40
55
55
-15VL,VLL
Min Max
150
100
0
120
120
120
50
0
0
50
50
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 MITSUBISHI
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1997-1/21
MITSUBISHI LSIs
M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,
-70VLL,-10VLL,-12VLL,-15VLL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~16
ta(A)
tv (A)
ta (S1)
S1
(Note 3)
tdis (S1)
(Note 3)
S2
OE
DQ1~8
W = "H" level
(Note 3)
(Note 3)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tdis (S2)
(Note 3)
tdis (OE)
DATA VALID
(Note 3)
Write cycle (W control mode)
A0~16
tCW
S1
S2
OE
W
DQ1~8
5
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten (W)
ten(OE)
DATA IN
STABLE
tsu (D)
th (D)
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(Note 3)
(Note 3)