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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
FEATURE
Type
M5M5256DFP,VP,RV-10VLL
M5M5256DFP,VP,RV-12VLL
M5M5256DFP,VP,RV-15VLL
M5M5256DFP,VP,RV-10VXL
M5M5256DFP,VP,RV-12VXL
M5M5256DFP,VP,RV-15VXL
Access Power supply current
time Active Stand-by
(max) (max) (max)
100ns
120ns
150ns
100ns
120ns
150ns
20mA
(Vcc=3.6V)
12µA
(Vcc=3.6V)
2.4µA
(Vcc=3.6V)
0.05µA
(Vcc=3.0V,
Typical)
•Single +2.7~3.6V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current··········0.05µA(typ.)
PACKAGE
M5M5256DFP : 28 pin 450 mil SOP
M5M5256DVP,RV : 28pin 8 X 13.4 mm2 TSOP
APPLICATION
Small capacity memory units
PIN CONFIGURATION (TOP VIEW)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vcc
27 /W
26 A13
25 A8
24 A9
23 A11
22 /OE
21 A10
20 /S
19 DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
Outline 28P2W-C (DFP)
22 /OE
23 A11
24 A9
25 A8
26 A13
A10 21
/S 20
DQ8 19
DQ7 18
DQ6 17
27 /W
28Vcc
1 A14
2 A12
3 A7
4 A6
5 A5
6 A4
7 A3
M5M5256DVP
DQ5 16
DQ415
GND 14
DQ313
DQ212
DQ111
A0 10
A1 9
A2 8
Outline 28P2C-A (DVP)
7 A3
A2 8
6 A4
A1 9
5 A5
A0 10
4 A6
DQ1 11
3 A7
DQ2 12
2 A12
DQ3 13
1 A14 M5M5256DRV GND 14
28 Vcc
DQ4 15
27 /W
DQ5 16
26 A13
DQ6 17
25 A8
DQ7 18
24 A9
DQ8 19
23 A11
22 /OE
/S 20
A10 21
Outline 28P2C-B (DRV)
MITSUBISHI
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
/S /W /OE
Mode
H X X Non selection
L LX
Write
L HL
Read
L HH
DQ
High-impedance
DIN
DOUT
High-impedance
Icc
Stand-by
Active
Active
Active
BLOCK DIAGRAM
ADDRESS
INPUT
A8
A 13
A 14
A 12
A7
A6
A5
A4
A3
25
26
1
22
3
4
5
6
7
A2
A1
A0
A 10
A 11
A9
8
9
10
21
23
24
WRITE CONTROL
INPUT /W
CHIP SELECT
INPUT /S
OUTPUT ENABLE /OE
INPUT
27
20
22
32768 WORD
X 8BIT
(512 ROWS X
512 COLUMNS)
CLOCK
GENERATOR
MITSUBISHI
ELECTRIC
11 DQ1
12 DQ2
13 DQ3
15 DQ4
16 DQ5
17 DQ6
18 DQ7
19 DQ8
DATA I/O
28 VCC
(3V)
14 GND
(0V)
2

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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO Output voltage
Pd Power dissipation
Topr Operating temperature
Tstg Storage temperature
* -3.0V in case of AC ( Pulse width 30ns )
Conditions
With respect to GND
Ta=25°C
Ratings
-0.3*~4.6
-0.3*~Vcc+0.3
(Max 4.6)
0~Vcc
700
0~70
-65~150
Unit
V
V
V
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol
Parameter
Test conditions
VIH High-level input voltage
VIL
VOH1
Low-level input voltage
High-level output voltage 1 IOH=-0.5mA
VOH2 High-level output voltage 2 IOH=-0.05mA
VOL Low-level output voltage IOL=1mA
II Input current
VI=0~Vcc
IO Output current in off-state /S=VIH or or /OE=VIH,
VI/O=0~Vcc
Icc1
Active supply current
(AC, MOS level )
/S0.2V,
Min.
cycle
Other inputs<0.2V or >Vcc-0.2V
Output-open Min. cycle
1MHz
Icc2
Active supply current
(AC, TTL level )
/S=VIL,
other inputs=VIH or VIL
Output-open Min. cycle
Min.
cycle
1MHz
Limits
Min Typ
2.0
Max
Vcc
+0.3
-0.3*
0.6
2.4
Vcc
-0.5
0.4
±1
±1
11 20
1.5 3
11 20
1.5 3
Icc3 Stand-by current
/SVcc-0.2V,
other inputs=0~Vcc
-VLL
-VXL
12
0.05 2.4
Icc4 Stand-by current
/S=VIH,other inputs=0~Vcc
0.33
* -3.0V in case of AC ( Pulse width 30ns )
Unit
V
V
V
V
V
uA
uA
mA
mA
uA
mA
CAPACITANCE (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol
Parameter
Test conditions
CI Input capacitance
CO Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
Limits
Min Typ Max
6
8
Unit
pF
pF
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level···················VIH=2.2V,VIL=0.4V
Input rise and fall time··········5ns
Reference level····················VOH=VOL=1.5V
Output loads·························Fig.1,CL=30pF (-10VLL,-10VXL )
DQ
CL=50pF (-12VLL,-12VXL )
CL=100pF (-15VLL,-15VXL )
CL=5pF (for ten,tdis)
(Including
CL
scope and JIG)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
Limits
-10VLL, VXL -12VLL, VXL -15VLL, VXL
Min Max Min Max Min Max
100 120 150
100 120 150
100 120 150
50 60 75
30 35 40
30 35 40
10 10 10
10 10 10
10 10 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
Symbol
Parameter
-10VLL, VXL -12VLL, VXL -15VLL, VXL
Min Max Min Max Min Max
tCW Write cycle time
100 120 150
tw(W) Write pulse width
70 80 90
tsu(A) Address setup time
000
tsu(A-WH) Address setup time with respect to /W high 80
tsu(S) Chip select setup time
80
90 100
90 100
tsu(D)
th(D)
trec(W)
Data setup time
Data hold time
Write recovery time
40 45 50
000
000
tdis(W)
tdis(OE)
ten(W)
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
30 35 40
30 35 40
10 10 10
ten(OE) Output enable time from /OE low
10 10 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~14
ta(A)
tv (A)
/S
/OE
(Note 3)
(Note 3)
ta (S)
ta (OE)
ten (OE)
ten (S)
tdis (S)
(Note 3)
tdis (OE)
(Note 3)
DQ1~8
/W = "H" level
DATA VALID
Write cycle (/W control mode)
A0~14
tCW
/S
/OE
/W
DQ1~8
(Note 3)
tsu (S)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
(Note 3)
tdis (W)
ten(OE)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
(Note 3)
(Note 3)
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