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revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5408B is a family of 4-Mbit static RAMs organized as
524,288-words by 8-bit, fabricated by Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5408B is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic
TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of
TSOPs and two types of STSOPs are available , M5M5408BTP
(normal-lead-bend TSOP) , M5M5408BRT (reverse-lead-bend
TSOP) , M5M5408BKV (normal-lead-bend STSOP) and
M5M5408BKR (reverse-lead-bend STSOP). These two types
TSOPs and two types STSOPs are suitable for a surface mounting
on double-sided printed circuit boards.
From the point of operating temperature, the family is divided
into three versions; "Standard", "W-version", and "I-version". Those
are summarized in the part name table below.
• Single +5V power supply
• Small stand-by current: 0.4µA(3V,typ.)
• No clocks, No refresh
• Data retention supply voltage=2.0V to 5.5V
• All inputs and outputs are TTL compatible.
• Easy memory expansion by S
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Process technology: 0.25µm CMOS
• Package:
M5M5408BFP: 32 pin 525 mil SOP
M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
M5M5408BKV/KR: 32 pin 8mm x 13.4mm STSOP
PART NAME TABLE
Version,
Operating
temperature
Part name
(## stands for "FP","TP",
"RT","KV"or"KR")
M5M5408B## -55L
Standard
0 ~ +70°C
M5M5408B## -70L
M5M5408B## -10L
M5M5408B## -55H
M5M5408B## -70H
M5M5408B## -10H
M5M5408B## -55LW
W-version
-20 ~ +85°C
M5M5408B## -70LW
M5M5408B## -10LW
M5M5408B## -55HW
M5M5408B## -70HW
M5M5408B## -10HW
I-version
-40 ~ +85°C
M5M5408B## -55LI
M5M5408B## -70LI
M5M5408B## -10LI
M5M5408B## -55HI
M5M5408B## -70HI
M5M5408B## -10HI
Power
Supply
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
* "typical" parameter is sampled, not 100% tested.
Access
time
max.
55ns
70ns
100ns
55ns
70ns
100ns
55ns
70ns
100ns
55ns
70ns
100ns
55ns
70ns
100ns
55ns
70ns
100ns
Stand-by current Icc(PD), Vcc=3.0V
typical *
Ratings (max.)
25°C
70°C
85°C
Active
current
Icc1
(5.0V, typ.)
--- 50µA ---
0.4µA
---
0.4µA
10µA
---
---
---
100µA
20µA
50mA
(10MHz)
25mA
(1MHz)
--- --- 100µA
0.4µA
---
20µA
MITSUBISHI ELECTRIC
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revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
(0V) GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC (5V)
31 A15
30 A17
29 W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 S
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
Outline 32P2M-A (FP)
32P3Y-H (TP)
(5V) VCC
A15
A17
W
A13
A8
A9
A11
OE
A10
S
DQ8
DQ7
DQ6
DQ5
DQ4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1 A18
2 A16
3 A14
4 A12
5 A7
6 A6
7 A5
8 A4
9 A3
10 A2
11 A1
12 A0
13 DQ1
14 DQ2
15 DQ3
16 GND (0V)
Outline 32P3Y-J (RT)
A11 1
A9 2
A8 3
A13 4
W
A18
A15
Vcc
5
6
7
8
A17 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
M5M5408BKV
Outline 32P3K-B
32 OE
31 A10
30 S
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
A17 9
Vcc 8
A15 7
A18 6
W5
A13 4
A8 3
A9 2
A11 1
M5M5408BKR
Outline 32P3K-C
17 A3
18 A2
19 A1
20 A0
21 DQ1
22 DQ2
23 DQ3
24 GND
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
30 S
31 A10
32 OE
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revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT,KV,KR is organized as 524,288-
words by 8-bit. These devices operate on a single +5.0V
power supply, and are directly TTL compatible to both input
and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
A write operation is executed during the S low and W low
overlap time. The address(A0~A18) must be set up before
the write cycle
A read operation is executed by setting W at a high level
and OE at a low level while S are in an active state(S=L).
When setting S at a high level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips. Setting the OE at a high
level,the output stage is in a high-impedance state, and the
data bus contention problem in the write cycle is eliminated.
The power supply current is reduced as low as 0.4µA(25°C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure
or power-down operation in the non-selected mode.
FUNCTION TABLE
S W OE
HXX
LLX
L HL
L HH
Mode
Non selection
Write
Read
Read
BLOCK DIAGRAM
M5M5408B
FP/TP/RT
M5M5408BKV/KR
A4 8
A5 7
A6 6
A7 5
A12 4
A14 3
A16 2
A17 30
A18 1
A15 31
16
15
14
13
12
11
10
9
6
7
A10 23
A11 25
A9 26
A8 27
A13 28
31
1
2
3
4
DQ
High-impedance
Data input (D)
Data output (Q)
High-impedance
Icc
Standby
Active
Active
Active
MEMORY ARRAY
524288 WORDS
x 8 BITS
CLOCK
GENERATOR
A0 12
A1 11
A2 10
A3 9
20
19
18
17
Pin Function
A0 ~ A18 Address input
DQ1 ~ DQ8 Data input / output
S Chip select input
W Write control input
OE Output inable input
Vcc Power supply
GND Ground supply
M5M5408BKV/KR
21
22
23
25
26
27
28
29
M5M5408B
FP/TP/RT
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
20 DQ7
21 DQ8
5 29 W
30 22 S
32 24 OE
8 32 VCC
(3V)
24 16 GND
(0V)
MITSUBISHI ELECTRIC
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revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
VO
Pd
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
Ta temperature
Tstg Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Standard (-L, -H)
W-version (-LW, -HW)
I-version (-LI, -HI)
Ratings
-0.3* ~ +7
-0.3* ~ Vcc + 0.3
0 ~ Vcc
700
0 ~ +70
-20 ~ +85
-40 ~ +85
-65 ~150
Units
V
mW
°C
°C
* -3.0V in case of AC (Pulse width 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
Conditions
VIH
VIL
VOH1
VOH2
VOL
II
IO
Icc1
Icc2
High-level input voltage
Low-level input voltage
High-level output voltage 1 IOH= -1mA
High-level output voltage 2 IOH= -0.1mA
Low-level output voltage IOL=2mA
Input leakage current
VI =0 ~ Vcc
Output leakage current S=VIH or OE=VIH, VI/O=0 ~ Vcc
Active supply current
( AC,MOS level )
S 0.2V Output-open
Other inputs 0.2V or Vcc-0.2V
Active supply current
( AC,TTL level )
S=VIL Output-open
Other inputs=VIH or VIL
Icc3 Stand by supply current
( AC,MOS level )
S Vcc-0.2V
Other inputs=0~Vcc
Icc4 Stand by supply current
( AC,TTL level )
S=V ,Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=5.0V and Ta=25°C
Limits
Min Typ Max
2.2 Vcc+0.3V
-0.3 *
0.8
2.4
Vcc-0.5V
0.4
±1
±1
minimum cycle
f= 1MHz
-
-
50 80
25 30
minimum cycle
f= 1MHz
-LW, -LI
-L
-HW, -HI
-
-
-
-
-
60 90
30 40
- 200
- 100
0.4 40
-H - 0.4 20
Units
V
µA
mA
µA
- - 3 mA
* -3.0V in case of AC (Pulse width 50ns)
CAPACITANCE
Symbol Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
(Vcc=5.0V±10%, unless otherwise noted)
Limits
Min Typ Max
8
10
Units
pF
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revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=5.0V±10%, unless otherwise noted)
(1) TEST CONDITIONS
Supply voltage
Input pulse
Input rise time and fall time
Reference level
Output loads
5.0V
VIH=2.4V,VIL=0.6V (FP,TP,RT,KV,KR-70,-10 )
VIH=3.0V,VIL=0V (FP,TP,RT,KV,KR-55 )
5ns
VOH=VOL=1.5V
Transition is measured ±500mV from
steady state voltage.(for ten,tdis)
Fig.1, CL=100pF (FP,TP,RT,KV,KR-70,-10 )
CL=30pF (FP,TP,RT,KV,KR-55 )
CL=5pF (for ten,tdis)
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
Read cycle time
Address access time
ta(S) Chip select access time
ta(OE) Output enable access time
tdis(S) Output disable time after S high
tdis(OE) Output disable time after OE high
ten(S)
ten(OE)
tV(A)
Output enable time after S low
Output enable time after OE low
Data valid time after address
M5M5408BFP,TP,RT,
KV,KR-55
Min Max
55
55
55
25
20
20
10
5
10
1.8k
DQ
990CL
CL Including scope and
jig capacitance
Fig.1 Output load
Limits
M5M5408BFP,TP,RT, M5M5408BFP,TP,RT,
KV,KR-70
KV,KR-10
Min Max Min Max
70 100
70 100
70 100
35 50
25 35
25 35
10 10
55
10 10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
Parameter
tCW Write cycle time
tw(W) Write pulse width
tsu(A)
Address set up time
tsu(A-WH) Address set up time with respect to W high
tsu(S)
tsu(D)
Chip select set up time
Data set up time
th(D)
Data hold time
trec(W) Write recovery time
tdis(W) Output disable time after W low
tdis(OE) Output disable time after OE high
ten(W) Output enable time after W high
ten(OE) Output enable time after OE low
M5M5408BFP,TP,RT,
KV,KR-55
Min Max
55
40
0
50
50
25
0
0
20
20
5
5
Limits
M5M5408BFP,TP,RT,
KV,KR-70
Min Max
M5M5408BFP,TP,RT,
KV,KR-10
Min Max
70 100
50 60
00
60 80
60 80
30 35
00
00
25 35
25 35
55
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI ELECTRIC
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