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1998.11.30 Ver.B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M54R01AJ is a family of 4194304-word by 1-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
FEATURES
•Fast access time
M5M54R01AJ-12 ... 12ns(max)
M5M54R01AJ-15 ... 15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
A0 1
A1 2
address
A2 3
inputs
A3 4
A4 5
chip select
input
A5 6
S7
(3.3V) VCC 8
(0V) GND 9
data inputs D 10
write control W 11
input
A6 12
address
inputs
A7 13
A8 14
A9 15
A10 16
Outline
32P0K
32 A21
31 A20
30 A19
address
29 A18 inputs
28 A17
27 A16
26 OE
output enable
input
25 GND (0V)
24 VCC (3.3V)
23 Q data outputs
22 A15
21 A14
20 A13
19 A12
address
inputs
18 A11
17
B1/B4
byte control
input
APPLICATION
High-speed memory units
BLOCK DIAGRAM
address
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 12
A7 13
A8 14
A9 15
S7
W 11
OE 26
B1/B4 17
PACKAGE
M5M54R01AJ
: 32pin 400mil SOJ
MEMORY ARRAY
1024 ROWS
4096 COLUMNS
23
Q
data
outputs
COLUMN I/O CIRCUITS
COLUMNCOLUMN ADDRESS
ADDRESS DECODERS
DECODERS
COLUMN INPUT BUFFERS
16 18 19 20 21 22 27 28 29 30 31 32
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
address inputs
10
D
data
inputs/
8 VCC (3.3V)
24
9
GND(0V)
25
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M54R01AJ is determined by a
combination of the device control inputs S, W and OE. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S. The address must be set-up before the write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time relative to
these edge to be maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level, the output
stage is in a high impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and OE at a
low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-selectable mode
in which both reading and writing are disable. In this mode, the
output stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by S.
Signal-S controls the power-down feature. When S goes high,
power dissapation is reduced extremely. The access time from S is
equivalent to the address access time.
The RAM works with an organization of 4194304-word by 1bit,
when B1/B4 is low of floating. And an organization of 1048576-word
by 4bit is also obtained for reducing the test time,when B1/B4 is
high. The pin configuration and function is as same as
M5M54R04AJ.
FUNCTION TABLE
B1/B4 S W OE
L HXX
L LLX
L L HL
L L HH
Mode
Non selection
Write
Read
D
High-impedance
Din
High-impedance
High-impedance
Q
High-impedance
High-impedance
Dout
High-impedance
Icc
Stand by
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
V cc Supply voltage
- 2.0 *~ 4.6
V
VI Input voltage
VO Output voltage
With respect to GND
- 2.0*~ VCC+0.5
- 2.0*~ VCC
V
V
Pd Power dissipation
Ta=25°C
1000
mW
Topr
Operating temperature
0 ~ 70
°C
Tstg(bias) Storage temperature(bias)
- 10 ~ 85
°C
Tstg Storage temperature
- 65 ~ 150
°C
* Pulse width3ns, In case of DC: - 0.5V
DC
ELECTRICAL
CHARACTERISTICS
(Ta=0
~
70°C,
+10%
Vcc=3.3V - 5%
,unless
otherwise
noted)
Symbol
Parameter
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage IOH= - 4mA
VOL Low-level output voltage IOL = 8mA
I I Input current
VI= 0 ~ Vcc
I OZ
Output current in off-state
VI(S)=VIH
VI/O= 0 ~ Vcc
Condition
Limits
Min Typ Max Unit
2.0 Vcc+0.3 V
0.8 V
2.4 V
0.4 V
2 uA
2 uA
Active supply current
I CC1 (TTL level)
VI(S)=VIL
other inpus=VIH or VIL
Output-open(duty 100%)
12ns cycle
AC
15ns cycle
DC
180
160 mA
90
Stand by current
I CC2 (TTL level)
I CC3 Stand by current
VI(S)=VIH
VI(S)=Vcc0.2V
other inputs VI0.2V
or VI Vcc - 0.2V
12ns cycle
AC
15ns cycle
DC
Note 1: Direction for current flowing into an IC is positive (no mark).
70
60 mA
40
10 mA
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MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
CAPACITANCE
(Ta=0~70°C,
Vcc=3.3V
+10%
-5%
,unless otherwise noted)
Symbol
Parameter
Test Condition
CI Input capacitance
V I =GND, V I =25mVrms,f=1MHz
CO Output capacitance
V O=GND, V O=25mVrms,f=1MHz
Note 2: CI,CO are periodically sampled and are not 100% tested.
Limit
Min Typ Max Unit
8 pF
8 pF
AC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C,
Vcc=3.3V
+10%
-5%
,unless
otherwise
noted)
(1)MEASUREMENT CONDITION
Input pulse levels .................................... VIH=3.0V, VIL=0.0V
Input rise and fall time .................................................... 3ns
Input timing reference levels ........................ VIH=1.5V, VIL=1.5V
Output timing reference levels ................. VOH =1.5V, VOL=1.5V
Output loads ........................................................ Fig.1,Fig.2
OUTPUT Z0=50
RL=50
VL=1.5V
DQ
Fig.1 Output load
5.0V
480
DQ 5pF
255(including
scope and JIG)
Fig.2 Output load for ten, t dis
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(2)READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tv(A)
tPU
tPD
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address change
Power-up time after chip selection
Power-down time after chip selection
MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
Limits
M5M54R01AJ-12 M5M54R01AJ-15
Min Max Min Max
12 15
12 15
12 15
67
0607
0607
33
11
33
00
12 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tw(W)
tsu(A)1
tsu(A)2
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
tsu(A-WH)
Write cycle time
Write pulse width (OE low)
Write pulse width(OE high)
Address setup time(W)
Address setup time(S)
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
Address to W High
Limits
M5M54R01AJ-12 M5M54R01AJ-15
Min Max Min Max
12 15
12 15
10 10
00
00
10 10
67
00
11
0607
0607
00
00
10 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M54R01AJ-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~21
VIH
VIL
tv(A)
Q
VOH
PREVIOUS DATA VALID
VOL
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv(A)
DATA VALID
Read cycle 2 (Note 3)
VIH
S VIL
t CR
ta(S)
(Note 4)
ten(S)
(Note 4)
tdis(S)
Q VOH
VOL
ICC1
Icc
ICC2
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
VIH
OE VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4) ten(OE)
Q VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
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