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MITSUBISHI LSIs
M5M54R01J-12,-15
1997.11.20 Rev.F
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M54R01J is a family of 4194304-word by 1-bit static PIN CONFIGURATION (TOP VIEW)
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
The M5M54R01J is offered in a 32-pin plastic small outline J-
lead package(SOJ).
These device operate on a single 5V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M54R01J-12 •••• 12ns(max)
M5M54R01J-15 •••• 15ns(max)
• Low power dissipation Active •••••••••• 450mW(typ)
Stand by •••••••••• 5mW(typ)
• Single +5V power supply
• Fully static operation : No clocks, No refresh
• Test mode is available
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
A0 1
address
inputs
A1 2
A2 3
A3 4
A4 5
chip select
input
A5 6
S7
(5V) VCC 8
(0V) GND 9
data inputs D 10
write control W 11
input
A6 12
address
inputs
A7 13
A8 14
A9 15
A10 16
Outline
32 A21
31 A20
30 A19
29 A18
address
inputs
28 A17
27 A16
26 OE
output enable
input
25 GND (0V)
24 VCC (5V)
23 Q data outputs
22 A15
21 A14
20 A13
19 A12
address
inputs
18 A11
17
B1/B4
byte control
input
32P0K(SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
address
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 12
A7 13
A8 14
S7
W 11
OE 26
B1/B4 17
PACKAGE
32pin 400mil SOJ
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN I/O CIRCUITS
COLUMNCOLUMN ADDRESS
ADDRESS DECODERS
DECODERS
COLUMN INPUT BUFFERS
15 16 18 19 20 21 22 27 28 29 30 31 32
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
address
inputs
MITSUBISHI
ELECTRIC
23
Q
data
outputs
10
D
data
inputs/
8
VCC (5V)
24
9
GND (0V)
25
1

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MITSUBISHI LSIs
M5M54R01J-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M54R01J is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at a
high level, the output stage is in a high impedance state, and
the data bus
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and OE
at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-selectable
mode in which both reading and writing are disable. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
The RAM works with an organization of 4194304-word by 1
bit,when B1/B4 is low of floating. And an organization of 1048
576-word by 4bit is also obtained for reducing the test time,
when B1/B4 is high.
FUNCTION TABLE
S W OE
HXX
LLX
L HL
L HH
Mode
Non selection
Write
Read
D
High-impedance
Din
High-impedance
High-impedance
Q
High-impedance
High-impedance
Dout
High-impedance
Icc
Stand by
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V cc Supply voltage
VI Input voltage
VO Output voltage
Pd Power dissipation
T opr
Operating temperature
Tstg(bias) Storage temperature (bias)
Tstg Storage temperature
*Pulse width 20ns, In case of DC:-0.5V
Conditions
With respect to GND
Ta=25 C
Ratings
-3.5* ~ 7
-3.5 * ~ VCC+0.3
-3.5 * ~ VCC+0.3
1000
0 ~ 70
-10 ~ 85
-65 ~ 150
Unit
V
V
V
mW
C
C
C
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=5V±10% unless otherwise noted)
Symbol
Parameter
Condition
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage IOH =-4mA
VOL Low-level output voltage IOL= 8mA
I I Input current
V I = 0~Vcc
I OZ
Output current in off-state
VI (S)= VIH
VO= 0~Vcc
Active supply current
I CC1 (TTL level)
VI (S)= VIL
other inputs V IH or VIL
Output-open(duty 100%)
Stand by current
I CC2 (TTL level)
I CC3 Stand by current
VI (S)= VIH
VI (S)= Vcc0.2V
other inputs VI0.2V
or VIVcc-0.2V
Limits
Min Typ Max
Unit
2.2 Vcc+0.3 V
-0.3 0.8 V
2.4 V
0.4 V
2 µA
10 µA
12ns cycle
AC 15ns cycle
DC
12ns cycle
AC 15ns cycle
DC
160
150 mA
90 100
75
70 mA
50
1 10 mA
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M54R01J-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0 ~ 70 C, Vcc=5V±10% unless otherwise noted)
Symbol
Parameter
Test Condition
CI Input capacitance
V I =GND, V I =25mVrms,f=1MHz
CO Output capacitance
V O=GND, V O=25mVrms,f=1MHz
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc=5V,Ta=25 C
3: CI,CO are periodically sampled and are not 100% tested.
Limit
Min
Typ
Unit
Max
8 pF
8 pF
AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=5V±10% unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels •••••••••••••••••••••••• V IH=3.0V, V IL =0.0V
Input rise and fall time •••••••••••••••••••••••••••••••••••••• 3ns
Input timing reference levels •••••••••••• V IH=1.5V, V IL=1.5V
Output timing reference levels ••••••••••V OH=1.5V, V OL =1.5V
Output loads •••••••••••••••••••••••••••••••••••••••••• Fig1 ,Fig2
OUTPUT Z0=50
RL=50
VL=1.5V
Fig.1 Output load
Vcc
480
DQ 5pF
255
(including
scope and JIG)
Fig.2 Output load for t en, t dis
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(2)READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis (S)
tdis (OE)
ten(S)
ten (OE)
tv(A)
tPU
tPD
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address change
Power-up time after chip selection
Power-down time after chip selection
MITSUBISHI LSIs
M5M54R01J-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
Limits
M5M54R01J -12 M5M54R01J -15
Min Max Min Max
12 15
12 15
12 15
68
0 607
0 607
00
00
33
0
12
0
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
Write cycle time
Write pulse width
tsu(A)1 Address setup time(W)
tsu(A)2 Address setup time(S)
tsu(S)
Chip select setup time
tsu (D)
Data setup time
th(D)
Data hold time
trec(W) Write recovery time
tdis (W) Output disable time after W low
tdis (OE) Output disable time after OE high
ten (W) Output enable time after W high
ten(OE) Output enable time after OE low
tsu(A-WH) Address to W High
Limits
M5M54R01J -12 M5M54R01J -15
Min Max Min Max
12 15
10 12
00
00
10 12
67
00
11
06 07
060 7
00
00
10 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M54R01J-12,-15
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~21
VIH
VIL
Q VOH
VOL
tv (A)
PREVIOUS DATA VALID
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv (A)
DATA VALID
Read cycle 2 (Note 4)
VIH
S VIL
t CR
ta(S)
(Note 5)
ten (S)
(Note 5)
tdis(S)
Q VOH
VOL
ICC1
Icc
ICC2
W=H
OE=L
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
Note 4. Addresses valid prior to or coincident with S transition low.
5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6)
VIH
OE VIL
t CR
ta (OE)
(Note 5)
tdis(OE)
(Note 5) ten(OE)
Q VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
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