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1998.11.30 Ver.B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M54R04AJ is a family of 1048576-word by 4-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
FEATURES
•Fast access time
M5M54R04AJ-10 ... 10ns(max)
M5M54R04AJ-12 ... 12ns(max)
M5M54R04AJ-15 ... 15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
A0 1
A1 2
aindpduretsss
A2 3
A3 4
chip select
input
A4 5
S6
data inputs/
outputs(3.3V)
DQ1
VCC
7
8
(0V) GND 9
data inputs/
outputs
DQ2 10
write control W 11
input
A5 12
A6 13
address
inputs
A7 14
A8 15
A9 16
Outline
32 A19
31 A18
30 A17
29 A16
aindpduretsss
28 A15
27 OE
output enable
input
26 DQ4 data inputs/
25 GND (0V) outputs
24 VCC (3.3V)
23 DQ3
22 A14
data inputs/
outputs
21 A13
20 A12
19 A11
address
inputs
18 A10
17 NC
32P0K(SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
PACKAGE
M5M54R04AJ
: 32pin 400mil SOJ
adress
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 12
A6 13
A7 14
A8 15
A9 16
MEMORY ARRAY
1024 ROWS
4096 COLUMNS
7 DQ1
10 DQ2
23 DQ3
26 DQ4
data
inputs/
outputs
S6
W 11
OE 27
COLUMN I/O CIRCUITS
COLUMN ADDRESS
DECODERS
COLUMN INPUT BUFFERS
8
VCC (3.3V)
24
9
GND(0V)
25
18 19 20 21 22 28 29 30 31 32
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
address inputs
MITSUBISHI
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MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M54R04AJ is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S. The address must be set-up
before the write cycle and must be stable during the entire
cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-
selectable mode in which both reading and writing are
disable. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
FUNCTION TABLE
S W OE
Mode
HXX
Non selection
LLX
Write
L HL
Read
L HH
DQ
High-impedance
Din
Dout
High-impedance
Icc
Stand by
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
V cc Supply voltage
- 2.0 *~ 4.6
V
VI Input voltage
VO Output voltage
With respect to GND
- 2.0*~ VCC+0.5
- 2.0*~ VCC
V
V
Pd Power dissipation
Ta=25°C
1000
mW
Topr
Operating temperature
0 ~ 70
°C
Tstg(bias) Storage temperature(bias)
- 10 ~ 85
°C
Tstg Storage temperature
- 65 ~ 150
°C
* Pulse width3ns, In case of DC: - 0.5V
DC
ELECTRICAL
CHARACTERISTICS
(Ta=0
~
70°C,
+10%
Vcc=3.3V - 5%
,unless
otherwise
noted)
Symbol
Parameter
Condition
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage IOH= - 4mA
VOL Low-level output voltage IOL = 8mA
I I Input current
VI= 0 ~ Vcc
I OZ
Output current in off-state
VI(S)=VIH
VI/O= 0 ~ Vcc
Active supply current
I CC1 (TTL level)
VI(S)=VIL
other inpus=VIH or VIL
Output-open(duty 100%)
Stand by current
I CC2 (TTL level)
I CC3 Stand by current
VI(S)=VIH
VI(S)=Vcc0.2V
other inputs VI0.2V
or VI Vcc - 0.2V
Limits
Min Typ Max Unit
2.0 Vcc+0.3 V
0.8 V
2.4 V
0.4 V
2 uA
2 uA
10ns cycle
AC 12ns cycle
15ns cycle
DC
10ns cycle
AC 12ns cycle
15ns cycle
DC
190
180 mA
160
90
90
70 mA
60
40
10 mA
Note 1: Direction for current flowing into an IC is positive (no mark).
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MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
CAPACITANCE
(Ta=0~70°C,
Vcc=3.3V
+10%
-5%
,unless otherwise noted)
Symbol
Parameter
Test Condition
CI Input capacitance
V I =GND, V I =25mVrms,f=1MHz
CO Output capacitance
V O=GND, V O=25mVrms,f=1MHz
Note 2: CI,CO are periodically sampled and are not 100% tested.
Limit
Min Typ Max Unit
7 pF
8 pF
AC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C,
Vcc=3.3V
+10%
-5%
,unless
otherwise
noted)
(1)MEASUREMENT CONDITION
Input pulse levels .................................... VIH=3.0V, VIL=0.0V
Input rise and fall time .................................................... 3ns
Input timing reference levels ........................ VIH=1.5V, VIL=1.5V
Output timing reference levels ................. VOH =1.5V, VOL=1.5V
Output loads ........................................................ Fig.1,Fig.2
OUTPUT Z0=50
RL=50
VL=1.5V
DQ
Fig.1 Output load
5.0V
480
DQ 5pF
255(including
scope and JIG)
Fig.2 Output load for ten, t dis
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MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(2)READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tv(A)
tPU
tPD
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address change
Power-up time after chip selection
Power-down time after chip selection
M5M54R04AJ-10
Min Max
10
10
10
5
05
05
2
0
2
0
10
Limits
M5M54R04AJ-12
Min Max
12
12
12
6
06
06
3
1
3
0
12
M5M54R04AJ-15
Min Max
15
15
15
7
07
07
3
1
3
0
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tw(W)
tsu(A)1
tsu(A)2
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
tsu(A-WH)
Write cycle time
Write pulse width (OE low)
Write pulse width(OE high)
Address setup time(W)
Address setup time(S)
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
Address to W High
M5M54R04AJ-10
Min Max
10
10
8
0
0
8
5
0
1
05
05
0
0
8
Limits
M5M54R04AJ-12
Min Max
12
12
10
0
0
10
6
0
1
06
06
0
0
10
M5M54R04AJ-15
Min Max
15
15
10
0
0
10
7
0
1
07
07
0
0
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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MITSUBISHI LSIs
M5M54R04AJ-10,-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~19
VIH
VIL
DQ1~4 VOH
VOL
tv(A)
PREVIOUS DATA VALID
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv(A)
DATA VALID
Read cycle 2 (Note 3)
VIH
S VIL
t CR
ta(S)
(Note 4)
ten(S)
(Note 4)
tdis(S)
DQ1~4
VOH
VOL
ICC1
Icc
ICC2
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
VIH
OE VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4) ten(OE)
DQ1~4
VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
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