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1998.6.18 Ver.A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M564R16D is a family of 65536-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by LB
and UB.
FEATURES
•Fast access time M5M564R16DJ,TP-10 ... 10ns(max)
M5M564R16DJ,TP-12 ... 12ns(max)
M5M564R16DJ,TP-15 ... 15ns(max)
•Low power dissipation Active .................. 363mW(typ)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
•Separate control of lower and upper bytes by LB and UB
PIN CONFIGURATION (TOP VIEW)
A0
ADDRESS
INPUTS
A1
A2
A3
CHIP
SELECT
INPUTS
DATA
INPUTS/
OUTPUTS
A4
S
DQ1
DQ2
DQ3
DQ4
(3.3V) VCC
(0V) GND
DQ5
DATA
INPUTS/
OUTPUTS
WRITE
DQ6
DQ7
DQ8
CONTROL W
INPUT
A5
ADDRESS
INPUTS
A6
A7
A8
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A15
43
A14
ADDRESS
INPUTS
42 A13
41
OE
OUTPUT
INPUT
ENABLE
40 UB BYTE
39 LB CONTROL
INPUTS
38 DQ16
37 DQ15 DATA
36
DQ14
INPUTS/
OUTPUTS
35 DQ13
34 GND(0V)
33 VCC (3.3V)
32 DQ12
31 DQ11 DATA
30 DQ10 INPUTS/
29 DQ9 OUTPUTS
28 N.C
27 A12
26 A11 ADDRESS
25 A10
INPUTS
24 A9
23 N.C
Outline 44P0K(J)
44P3W-H(TP)
APPLICATION
PACKAGE
High-speed memory system
M5M564R16DJ : 44pin 400mil SOJ
M5M564R16DTP : 44pin 400mil TSOP(II)
FUNCTION
The operation mode of the M5M564R16D is
determined by a combination of the device control
inputs S, W, OE, LB, and UB. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with low level LB and/or low level UB and low
level S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
W, LB, UB or S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level,
the output stage is in a high impedance state, and the
data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and OE at a low level while LB and/or UB and S are in
an active
state. (LB and/or UB=L, S=L)
When setting LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and upper-
Byte are in a non-selectable mode.
When setting LB and UB at a high level or S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by LB, UB and S.
Signal-S controls the power-down feature. When S
goes high, power dissapation is reduced extremely.
The access time from S is equivalent to the address
access time.
MITSUBISHI
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION TABLE
S W OE LB UB
Mode
LHLL L
Read cycle All Bytes
DQ1~8
D OUT
L H L H L Read cycle Upper Bytes High-impedance
L H L L H Read cycle Lower Bytes
D OUT
L L XL L
Write cycle All Bytes
D IN
L L X H L Write cycle Upper Bytes High-impedance
LL
LH
LX
HX
XL
HX
XH
XX
H Write cycle Lower Bytes
D IN
X
Output disable
H
High-impedance
X Non selection High-impedance
DQ9~16
D OUT
D OUT
High-impedance
D IN
D IN
High-impedance
High-impedance
High-impedance
Icc
Active
Active
Active
Active
Active
Active
Active
Stand by
BLOCK DIAGRAM
ADDRESS
INPUTS
A0 1
A1 2
A2 3
A3 4
A4 5
A5 18
A6 19
A7 20
A8 21
CHIP SELECT
INPUTS
S
6
WRITE
CONTROL INPUT
W
17
OUTPUT
ENABLE INPUT
OE
41
UPPER BYTE
CONTROL INPUTS
UB
40
LOWER BYTE
CONTROL INPUTS
LB
39
18 512 MEMORY ARRAY
512 ROWS
2048 COLUMNS
2048
COLUMN I/O CIRCUITS
COLUMN ADDRESS
DECODERS
14
COLUMN INPUT BUFFERS
24 25 26 27 42 43 44
A9 A10 A11 A12 A13 A14 A15
ADDRESS INPUTS
7
8
9
10
13
14
15
16
DDDDDDDDQQQQQQQQ12345678
DATA
INPUTS/
OUTPUTS
29 DQ9
30
31
32
35
36
37
38
DDDDDQQQQQ1111101234
DQ15
DQ16
DATA
INPUTS/
OUTPUTS
11
33 VCC (3.3V)
12
GND (0V)
34
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V cc Supply voltage
V I Input voltage
V O Output voltage
P d Power dissipation
T opr
Operating temperature
Tstg(bias) Storage temperature(bias)
Conditions
With respect to GND
Ta=25°C
Ratings
- 2.0*~ 4.6
- 2.0*~ Vcc+0.5
- 2.0*~ Vcc
1000
0 ~ 70
- 10 ~ 85
Unit
V
V
V
mW
°C
°C
Tstg Storage temperature
- 65 ~ 150
°C
*Pulse width 5ns, In case of DC: - 0.5V
+10%
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V -5%,unless otherwise noted)
Symbol
Parameter
Condition
Min
Limits
Typ Max
Unit
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage IOH = - 4mA
2.0 Vcc+0.3 V
0.8 V
2.4 V
VOL Low-level output voltage IOL= 8mA
I I Input current
V I = 0 ~ Vcc
IOZ
Output current in off-state
VI (S)= VIH
VO= 0 ~ Vcc
0.4 V
2 uA
2 uA
Active supply current
I CC1 (TTL level)
VI (S)= VIL
other inputs V IH or VIL
Output-open(duty 100%)
AC(10ns cycle)
AC(12ns cycle)
AC(15ns cycle)
DC
200
195 mA
190
110 140
AC(10ns cycle)
70
I CC2
Stand-by supply current
(TTL level)
VI (S)= VIH
AC(12ns cycle)
AC(15ns cycle)
65 mA
60
DC 40
Stand-by current
I CC3 (MOS level)
VI (S)= Vcc - 0.2V
other inputs VI0.2V
or VIVcc - 0.2V
10 mA
Note 1: Direction for current flowing into an IC is positive (no mark).
CAPACITANCE
(Ta=0~70°C
,
Vcc=3.3V
+10%
-5% ,unless
otherwise
noted)
Symbol
Parameter
Test Condition
C I Input capacitance
CO Output capacitance
VI =GND,Vi =25mVrms,f=1MHz
Vo =GND,Vo =25mVrms,f=1MHz
Note 2: CI,CO are periodically sampled and are not 100% tested.
Min
Limit
Typ Max
Unit
6 pF
8 pF
AC
ELECTRICAL
CHARACTERISTICS
(Ta=
0~70
°C
,VCC=3.3V
+10%
-5%
,unless
otherwise
noted)
(1) MEASUREMENT CONDITION
Input pulse levels ................................... VIH=3.0V,VIL=0.0V
Input rise and fall time ................................................... 3ns
Input timing reference levels ...................... VIH=1.5V,VIL=1.5V
Output timing reference levels ................ VOH=1.5V, VOL=1.5V
Output loads ....................................................... Fig1 ,Fig2
OUTPUT
Z0=50
RL=50
VL=1.5V
DQ DQ
5.0V
480
2555pF
( )Including
scope and JIG
Fig.1 Output load
Fig.2 Output load for t en, t dis
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
ta(B)
tdis(S)
tdis(OE)
tdis(B)
ten(S)
ten(OE)
ten(B)
tv(A)
tPU
tPD
Read cycle time
Address access time
Chip select access time
Output enable access time
LB,UB access time
Output disable time after S high
Output disable time after OE high
Output disable time after LB,UB high
Output enable time after S low
Output enable time after OE low
Output enable time after LB,UB low
Data valid time after address change
Power-up time after chip selection
Power down time after chip selection
M5M564R16D-10
Min Max
10
10
10
5
5
05
05
05
4
3
3
4
0
10
Limits
M5M564R16D-12
Min Max
12
12
12
6
6
06
06
06
4
3
3
4
0
12
M5M564R16D-15
Min Max
15
15
15
7
7
07
07
07
4
3
3
4
0
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle
Symbol
Parameter
tCW
tw(W)
tsu(B)
tsu(A)1
tsu(A)2
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
ten(B)
tsu(A-WH)
tsu(A-SH)
tsu(A-BH)
Write cycle time
Write pulse width
LB,UB setup time
Address setup time(W)
Address setup time(S)
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
Output enable time after LB,UB low
Address to W High
Address to S High
Address to LB,UB High
M5M564R16D-10
Min Max
10
9
9
0
0
9
5
0
0
05
05
0
0
0
9
9
9
Limits
M5M564R16D-12
Min Max
12
10
10
0
0
10
6
0
0
06
06
0
0
0
10
10
10
M5M564R16D-15
Min Max
15
12
12
0
0
12
7
0
0
07
07
0
0
0
12
12
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~15
VIH
VIL
DQ1~16 VOH
VOL
tv(A)
PREVIOUS DATA VALID
W=H LB=L
S=L UB=L
OE=L
t CR
ta(A)
UNKNOWN
tv(A)
DATA VALID
Read cycle 2 (Note 3)
VIH
S VIL
t CR
ta(S)
(Note 4)
ten(S)
(Note 4)
tdis(S)
DQ1~16 VOH
VOL
ICC1
Icc
ICC2
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
W=H UB=L
OE=L LB=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
VIH
OE VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4) ten(OE)
DQ1~16 VOH
VOL
W=H UB=L
S=L LB=L
UNKNOWN
DATA VALID
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
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