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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

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Jan.10,2003 Ver. 2.1
M5M5J167KT - 70HI
MITSUBISHI LSIs
16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5J167KT is a f amily of low v oltage 16Mbit static RAMs
organized as 1048576-words by 16-bit / 2097152-words by 8-bit,
f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS
technology .
The M5M5J167KT is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are
the important design objectiv es.
The M5M5J167KT is made by stacked-micro-package technology
and two chips of 8Mbits SRAMs are assembled in one package.
By using this package technology , small package size can be
achiev ed f or highdensity SRAM.
The M5M5J167KT is packaged in a 52pin-µTSOP with the outline
of 10.79mm x 10.49mm, and pin pitch of 0.40mm. It giv es the
best solution f or a compaction of m ounting area as well as
f lexibility of wiring pattern of printed circuit boards.
The operating temperature range is -40 ~ +85°C
FEATURES
- Single 2.7~3.6V power supply
- Small stand-by current: 0.2µA (2.0V, ty p.)
- No clocks, No ref resh
- Data retention supply v oltage =2.0~3.6V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1# and BC2#
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prev ents data contention in the I/O bus
- By te f unction (x8 mode) av ailable by By te# & A-1.
- Process technology : 0.18µm CMOS
- Package: 52pin 10.79mm x 10.49mm µTSOP
[0.4mm pin pitch]
Operating
temperature
-40 ~ +85°C
Part name
Stand-by c urrent
Power Access time * Ty pical
Ratings (max.)
Supply
max. 25ºC 40ºC 25ºC 40ºC 70ºC 85ºC
M5M5J167KT -70HI 2.7 ~ 3.6V 70ns
2.0 2.4 10 16 40 80
Active
current
Icc1
(3.3V, Ty p.)
30mA
(10MHz)
5mA
(1MHz)
PIN CONFIGURATION
A15
A14
A13
A12
A11
A10
A9
A8
A19
S1#
W#
NC
NC
VCC
S2
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
10.49mm
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
52 A16
51 BYTE#
50 BC2#
49 GND
48 BC1#
47 DQ16/A-1
46 DQ8
45 DQ15
44 DQ7
43 DQ14
Pin Function
A0 ~ A18 Address input
42 DQ6
A19 Address input
41 DQ13 DQ1 ~ DQ16 Data input / output
40 DQ5
39 NC
38 DQ12
S1# Chip select input 1
S2 Chip select input 2
37 DQ4
W# Write control input
36 DQ11
35 DQ3
34 DQ10
33 DQ2
OE#
BC1#
BC2#
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
32 DQ9
31 DQ1
30 OE#
BYTE#
Vcc
By te (x8 mode) enable input
Power supply
29 GND
28 NC
GND Ground supply
27 A0 Outline: 52PTG-A
N C : No Connection
1

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Jan.10,2003 Ver. 2.1
M5M5J167KT - 70HI
MITSUBISHI LSIs
16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5J167KT is organized as 1048576-words by 16-
bit / 2097152-words by 8-bit. These dev ices operate on a
single +2.7~3.6V power supply , and are directly TTL
compatible to both input and output. Its f ully static circuit
needs no clocks and no ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W#,
OE# and BY TE#. Each mode is summarized in the f unction
table. The address select A19 can select either one
8MSRAM chip or another 8MSRAM chip.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address (A-1~A19 :
By te mode, A0~A19 : Word mode) must be set up bef ore
the write cy c le and must be stable during the entire cy cle.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S1#and S2 are in an activ e state (S1#=L, S2=H).
When setting BYTE# at a low lev el, the f unction will be
in the x8 mede, which is, DQ1-8 are av ailable and DQ9-16
are not av ailable. In the x8 mode, A-1 is used as the
additional address. During the activ e f unction f or x8 mode,
BC1# BC2# must be low lev el.
When setting BC1# and BC2# at a high lev el or S1# at
a high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by
BC1#, BC2# and S1#, S2.
The power supply c urrent is reduced as low as 0.2µA
(25°C, ty pical), and the memory data can be held at +2.0V
power supply , enabling battery back-up operation during
power f ailure or power-down operation in the non-selected
mode.
FUNCTION TABLE
S1# S2 BYTE# BC1# BC2# W# OE#
Mode
H H X X X X X Non selection
X L X X X X X Non selection
X X H H H X X Non selection
LHHLHL X
Write
L HH L HH L
Read
L HH L HHH
-------
LHHHL L X
Write
L HHH L H L
Read
L HHH L HH
-------
LHHL L L X
Write
LHHL LHL
Read
LHHL LHH
-------
LHL L L LX
Write
LHL L LHL
Read
LHL L LHH
-------
Note1 : "H" and "L" in this table mean VIH and VIL, respectiv ely .
Note2 : "X" in this table should be "H" or "L".
DQ1~8 DQ9~15 DQ16
High-Z High-Z High-Z
High-Z High-Z High-Z
High-Z High-Z High-Z
Din High-Z High-Z
Dout High-Z High-Z
High-Z High-Z High-Z
High-Z Din
Din
High-Z Dout Dout
High-Z High-Z High-Z
Din Din Din
Dout Dout Dout
High-Z High-Z High-Z
Din High-Z A-1
Dout High-Z A-1
High-Z High-Z A-1
Icc
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
2

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Jan.10,2003 Ver. 2.1
M5M5J167KT - 70HI
MITSUBISHI LSIs
16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM
BLOCK DIAGRAM
A0
A18
S2
S1#
BC1#
BC2#
BYTE#
W#
OE#
A19
524288WORDS X
16 BITS
or
1048576WORDS X
8 BITS
CLOCK
GENERATOR
x8/x16
Switching
circuit
8MS(1)
DQ1
DQ 8
DQ9
DQ16 /
A-1
VCC
GND
8MS(2)
3

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Jan.10,2003 Ver. 2.1
M5M5J167KT - 70HI
MITSUBISHI LSIs
16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Vcc Supply v oltage
VI Input v oltage
With respect to GND
With respect to GND
VO Output v oltage
With respect to GND
Pd Power dissipation
Ta = 25°C
T a Operating temperature
T stg Storage temperature
Ratings
- 0.3* ~ +4.6
- 0.3* ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
700
-40 ~ +85
- 65 ~ +150
* -3.0V in case of AC (Pulse<=width
Units
V
mW
ºC
ºC
30ns)
DC ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC Vcc=2.7V~3.6V,unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min
Ty p Max
Units
VIH High-lev el input v oltage
2.2 Vcc+0.2V
VIL
VOH
V OL
II
IO
Icc1
Icc2
Icc3
Icc4
Low-lev el input v oltage
High-level output voltage
IOH= - 0.5mA
Low-lev el output v oltage IOL= 2.0mA
Input leakage current VI =0 ~ Vcc
Output leakage current BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc
Activ e supply c urrent
( AC,MOS lev el )
BC1# and BC2# < 0.2V, S1# < 0.2V, S2 >Vcc-0.2V
other inputs < 0.2V or > Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Activ e supply c urrent
( AC,TTL lev el )
BC1# and BC2#=V IL , S1#=V IL ,S2=V IH
other pins =V IH or VIL
Output - open (duty 100%)
f = 10MHz
f = 1MHz
(1) S1# > Vcc - 0.2V and S2 > Vcc - 0.2V,
BYTE# > Vcc - 0.2V or < 0.2V,
other inputs = 0 ~ Vcc
(2)S2 < 0.2V,
Stand by s upply current
BYTE# > Vcc - 0.2V or < 0.2V,
other inputs = 0 ~ Vcc
( AC,MOS lev el ) (3) BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
BYTE# > Vcc - 0.2V or < 0.2V,
A19 > Vcc - 0.2V or < 0.2V
other inputs = 0 ~ Vcc
Stand by s upply current
BC1# and BC2# =VIH or S1# =VIH or S2=VIL
BYTE# > Vcc - 0.2V or < 0.2V,
( AC,TTL lev el )
A19 =V IH or V IL
Other inputs= 0 ~ Vcc
~ +25°C
~ +40°C
~ +70°C
~ +85°C
- 0.2 *
2.4
-
-
-
-
-
-
-
-
-
30
5
30
5
2.0
2.4
-
-
-
0.6
0.4
±1
±1
50
15
50
15
10
16
40
80
2.0
V
µA
mA
µA
mA
Note 3: Direction for current flowing into IC is indicated as positive (no mark)
* -1.0V in case of AC (Pulse width <= 30ns)
Note 4: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
CAPACITANCE (Ta=-40~+85ºC Vcc=2.7V~3.6V,unless otherwise noted)
Symbol
Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
Limits
Min Ty p Max
20
20
Units
pF
4