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Revision-A0.2E 29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
DESCRIPTION
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FEATURES
The M5M5V208A is a family of low voltage 2-Mbit static RAMs
organized as 262,144-words by 8-bit, fabricated by Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5V208A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
The M5M5V208A is packaged in 32-pin 8mm x 13.4mm STSOP
packages. Two types of STSOPs are available, M5M5V208AKV
(normal-lead-bend STSOP) and M5M5V208AKR (reverse-lead-bend
STSOP). These two types STSOPs are suitable for a surface
mounting on double-sided printed circuit boards.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
• Single 2.7 ~ 3.6V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current • • • • • • • • • • 0.3µA(typ.)
PACKAGE
PART NAME TABLE
M5M5V208AKV,KR : 32pin 8 X 13.4 mm TSOP
Version,
Operating
temperature
Part name
(## stands for"KV"or"KR")
Power
Supply
Standard
0 ~ +70°C
M5M5V208A## -55L
M5M5V208A## -70L
M5M5V208A## -55H
M5M5V208A## -70H
2.7 ~ 3.6V
2.7 ~ 3.6V
M5M5V208A## -55LW
W-version M5M5V208A## -70LW 2.7 ~ 3.6V
-20
~
+85°C
M5M5V208A##
M5M5V208A##
-55HW
-70HW
2.7
~
3.6V
M5M5V208A## -55LI
I-version M5M5V208A## -70LI
-40
~
+85°C
M5M5V208A## -55HI
M5M5V208A## -70HI
2.7 ~ 3.6V
2.7 ~ 3.6V
Access
time
max.
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
Stand-by current Icc(PD), Vcc=3.0V
typical *
Ratings (max.)
25°C 40°C 25°C 40°C 70°C 85°C
Active
current
Icc1
(3.0V, typ.)
--- --- --- --- 20µA ---
0.3µA ---
--- ---
0.3µA ---
1µA 3µA 8µA --- 20mA
(f=10MHz)
--- --- 20µA 50µA
3mA
1µA 3µA 8µA 24µA (f=1MHz)
--- --- --- --- 20µA 50µA
0.3µA --- 1µA 3µA 8µA 24µA
* "typical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW)
A11 1
A9 2
A8 3
A13 4
W5
S2 6
A15 7
Vcc 8
A17 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
M5M5V208AKV
Outline 32P3K-B(KV)
32 OE
31 A10
30 S1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
A17 9
Vcc 8
A15 7
S2 6
W5
A13 4
A8 3
A9 2
A11 1
M5M5V208AKR
Outline 32P3K-C(KR)
17 A3
18 A2
19 A1
20 A0
21 DQ1
22 DQ2
23 DQ3
24 GND
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
30 S1
31 A10
32 OE
MITSUBISHI ELECTRIC
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Revision-A0.2E 29.Jan.'99
MITSUBISHI LSIs
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208A is determined by a
combination of the device control inputs S1, S2, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and
OE at a low level while S1 and S2 are in an active state (S1
= L ,S2 = H).
When setting S1 at a high level or S2 at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S1 or S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
FUNCTION TABLE
S1 S2 W
X LX
H XX
L HL
L HH
L HH
OE Mode
X Non selection
X Non selection
X Write
L Read
H
DQ
High-impedance
High-impedance
D IN
D OUT
High-impedance
Icc
Standby
Standby
Active
Active
Active
BLOCK DIAGRAM
A4 8
A5 7
A6 6
A7 5
A12 4
A14 3
A16 2
A17 1
A15 31
*
16
15
14
13
12
11
10
9
7
262144 WORDS
X 8 BITS
512 ROWS
X 128 COLUMNS
X 32 BLOCKS
*
21 13 DQ1
22 14 DQ2
23 15 DQ3
25 17 DQ4
26 18 DQ5
27 19 DQ6
28 20 DQ7
29 21 DQ8
A0 12
A1 11
A2 10
A3 9
A10 23
A11 25
A9 26
A8 27
A13 28
20
19
18
17
31
1
2
3
4
CLOCK
GENERATOR
*Pin numbers inside dotted line show reverse-lead-bend sTSOP.
MITSUBISHI ELECTRIC
5 29 W
30 22 S1
6 30 S2
32 24 OE
8 32 VCC
(3V)
GND
24 16
(0V)
2

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Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO Output voltage
Pd Power dissipation
Topr Operating temperature
Tstr Storage temperature
* - 3.0V in case of AC ( Pulse width 30ns )
Conditions
With respect to GND
Ta=25°C
Standard
W - Version
I - Version
Ratings
- 0.5*~4.6
- 0.5* ~ Vcc + 0.5
(Max 4.6)
0 ~ Vcc
700
0 ~ 70
- 20 ~ 85
- 40 ~ 85
- 65 ~150
Unit
V
V
V
mW
°C
°C
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
VIH High-level input voltage
Test conditions
Limits
Min Typ
2.0
Max
Vcc
+0.3V
Unit
V
VIL
VOH1
VOH2
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
IOH= - 0.5mA
IOH= - 0.05mA
- 0.3*
2.4
Vcc
-0.5V
0.6 V
V
V
VOL Low-level output voltage IOL=2mA
II Input current
VI=0 ~ Vcc
0.4 V
±1 µA
IO
Output current in off-state
S1=VIH or S2=VIL or OE=VIH
VI/O=0 ~ Vcc
Icc1
Active supply current
(CMOS-level Input)
S1 0.2V, S2 Vcc-0.2V,
other inputs 0.2V
or Vcc-0.2V,output-open
f= 10MHz
f= 5MHz
f= 1MHz
Active supply current
Icc2 (TTL-level Input)
S1=VIL,S2=VIH,
other inputs=VIH or VIL
output-open
f= 10MHz
f= 5MHz
f= 1MHz
1) S2 0.2V,
-L
Icc3 Stand-by current
other inputs=0 ~ Vcc
or
2) S1 Vcc-0.2V,
S2 Vcc-0.2V
other inputs=0 ~ Vcc
-H ~+25°C
-HW ~+40°C
-HI ~+70°C
-HW / I ~+85°C
Icc4 Stand-by current
S1=VIH or S2=VIL,other inputs=0 ~ Vcc
±1
20 25
10 13
35
22 27
12 15
35
60
0.3 2
5
10
30
0.33
µA
mA
mA
µA
mA
* - 3.0V in case of AC ( Pulse width 30ns )
CAPACITANCE
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min Typ Max
Unit
CI Input capacitance
CO Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
8 pF
10 pF
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is for Vcc = 3V, Ta = 25°C
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Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
( Vcc= 2.7 ~ 3.6V, unless otherwise noted)
(1) MEASUREMENT CONDITIONS
Vcc ................................. 2.7 ~ 3.6V
Input pulse level ............. VIH=2.2V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ............... VOH=VOL=1.5V
Output loads ................... Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
1TTL
DQ
CL
including
scope and JIG
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
Limits
-55L,H -70L,H
Min Max Min Max
55 70
55 70
55 70
55 70
30 35
20 25
20 25
20 25
10 10
10 10
55
10 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
Parameter
tCW Write cycle time
tw(W) Write pulse width
tsu(A) Address setup time
tsu(A-WH) Address setup time with respect to W
tsu(S1) Chip select 1 setup time
tsu(S2) Chip select 2 setup time
tsu(D) Data setup time
th(D) Data hold time
trec(W) Write recovery time
tdis(W) Output disable time from W low
tdis(OE) Output disable time from OE high
ten(W) Output enable time from W high
ten(OE) Output enable time from OE low
Limits
-55L,H -55L,H
Min Max Min Max
55 70
45 55
00
50 65
50 65
50 65
25 30
00
0
20
0
25
20 25
55
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
(4) TIMING DIAGRAMS
Read cycle
A0~17
S1
(Note 3)
S2
(Note 3)
OE
(Note 3)
DQ1~8
W = "H" level
Write cycle (W control mode)
A0~17
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tCW
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
(Note 3)
S1
S2
OE
W
DQ1~8
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten(OE)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
(Note 3)
(Note 3)
MITSUBISHI ELECTRIC
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