M5M5V208RV-85LL-W.pdf 데이터시트 (총 7 페이지) - 파일 다운로드 M5M5V208RV-85LL-W 데이타시트 다운로드

No Preview Available !

'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W ,
-70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V208 is 2,097,152-bit CMOS static RAM organized as
262,144-words by 8-bit which is fabricated using high-performance
quadruple-polysilicon and double metal CMOS technology. The use
of thin film transistor(TFT) load cells and CMOS periphery results in a
high density and low power static RAM. The M5M5V208 is designed
for memory applications where high reliability, large storage, simple
interfacing and battery back-up are important design objectives.
The M5M5V208VP,RV,KV,KR are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).Two types of devices are available.
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy to
design a printed circuit board.
FEATURE
Type
Access Power supply current
time Active Stand-by
(max) (max) (max)
M5M5V208FP,VP,RV,KV,KR-70L 70ns
M5M5V208FP,VP,RV,KV,KR-85L
M5M5V208FP,VP,RV,KV,KR-10L
M5M5V208FP,VP,RV,KV,KR-12L
M5M5V208FP,VP,RV,KV,KR-70LL
85ns
100ns
120ns
70ns
27mA
(Vcc=3.6V)
60µA
(Vcc=3.6V)
M5M5V208FP,VP,RV,KV,KR-85LL
M5M5V208FP,VP,RV,KV,KR-10LL
M5M5V208FP,VP,RV,KV,KR-12LL
85ns
100ns
120ns
10µ A
(Vcc=3.6V)
• Single 2.7 ~ 3.6V power supply
• W-version: operating temperature of -20 to +70°C
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current · · · · · · · · · · 0.3µA(typ.)
PACKAGE
M5M5V208FP : 32 pin 525 mil SOP
M5M5V208VP,RV : 32pin 8 X 20 mm2 TSOP
M5M5V208KV,KR : 32pin 8 X 13.4 mm2 TSOP
APPLICATION
Small capacity memory units
Battery operating system
Handheld communiation tools
PIN CONFIGURATION (TOP VIEW)
A17 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
(0V)GND 16
32 VCC(3V)
31 A15
30 S2
29 W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 S1
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
A11 1
A9 2
A8 3
A13 4
W5
S2 6
A15 7
Vcc 8
A17 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
Outline 32P2M-A(FP)
M5M5V208VP,KV
-W
32 OE
31 A10
30 S1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 GND
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
Outline 32P3H-E(VP), 32P3K-B(KV)
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
A17 9
Vcc 8
A15 7
S2 6
W5
A13 4
A8 3
A9 2
A11 1
M5M5V208RV,KR
-W
17 A3
18 A2
19 A1
20 A0
21 DQ1
22 DQ2
23 DQ3
24 GND
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
30 S1
31 A10
32 OE
Outline 32P3H-F(RV), 32P3K-C(KR)
MITSUBISHI
ELECTRIC
1

No Preview Available !

'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W ,
-70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208 is determined by a
combination of the device control inputs S1, S2, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
FUNCTION TABLE
A read cycle is executed by setting W at a high level and
OE at a low level while S1 and S2 are in an active state (S1
= L ,S2 = H).
When setting S1 at a high level or S2 at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S1 or S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
S1 S2 W
X LX
H XX
L HL
L HH
L HH
OE Mode
X Non selection
X Non selection
X Write
L Read
H
DQ
High-impedance
High-impedance
D IN
D OUT
High-impedance
Icc
Standby
Standby
Active
Active
Active
BLOCK DIAGRAM
A4 8
A5 7
A6 6
A7 5
A12 4
A14 3
A16 2
A17 1
A15 31
*
16
15
14
13
12
11
10
9
7
262144 WORDS
X 8 BITS
512 ROWS
X 128 COLUMNS
X 32 BLOCKS
*
21 13 DQ1
22 14 DQ2
23 15 DQ3
25 17 DQ4
26 18 DQ5
27 19 DQ6
28 20 DQ7
29 21 DQ8
A0 12
A1 11
A2 10
A3 9
A10 23
A11 25
A9 26
A8 27
A13 28
20
19
18
17
31
1
2
3
4
CLOCK
GENERATOR
*Pin numbers inside dotted line show those of TSOP.
MITSUBISHI
ELECTRIC
5 29 W
30 22 S1
6 30 S2
32 24 OE
8 32 VCC
(3V)
24 16 GND
(0V)
2

No Preview Available !

'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR -70L-W , -85L -W, -10L-W , -12L-W ,
-70LL-W, -85LL-W, -10LL-W, -12LL-W
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO
Pd
Topr
Tstr
Output voltage
Power dissipation
Operating temperature
Storage temperature
* –3.0V in case of AC ( Pulse width 30ns )
Conditions
With respect to GND
Ta=25°C
Ratings
– 0.5*~4.6
– 0.5* ~ Vcc + 0.5
(Max 4.6)
0 ~ Vcc
700
– 20 ~ 70
– 65 ~150
Unit
V
V
V
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS
(Ta=20~70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min Typ Max
Unit
VIH
VIL
VOH1
VOH2
VOL
II
IO
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
IOH= –0.5mA
IOH= –0.05mA
Low-level output voltage
Input current
Output current in off-state
IOL=2mA
VI=0 ~ Vcc
S1=VIH or S2=VIL or OE=VIH
VI/O=0 ~ Vcc
2.0
–0.3*
2.4
Vcc
-0.5V
Vcc
+0.3V
0.6
0.4
±1
±1
V
V
V
V
V
µA
µA
Active supply current
Icc1
(CMOS-level Input)
S1 0.2V, S2Vcc-0.2V,
f= 10MHz
other inputs 0.2V
or Vcc-0.2V,output-open f= 5MHz
20 25
mA
10 13
Icc2 Active supply current
(TTL-level Input)
S1=VIL,S2=VIH,
other inputs=VIH or VIL
output-open
f= 10MHz
f= 5MHz
22 27
12 15
mA
1) S2 0.2V or
-L -20 ~ +70°C
60
Icc3 Stand-by current
2) S1 Vcc-0.2V,
-20 ~ +70°C
S2 Vcc-0.2V
-LL -20 ~ +40°C
other inputs=0 ~ Vcc
+25°C
10
1
0.3 0.6
µA
Icc4 Stand-by current
S1=VIH or S2=VIL,other inputs=0 ~ Vcc
0.33 mA
* –3.0V in case of AC ( Pulse width 30ns )
CAPACITANCE
(Ta=– 20 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min Typ Max
Unit
CI Input capacitance
CO Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
7 pF
9 pF
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is for Vcc = 3V, Ta = 25°C
MITSUBISHI
ELECTRIC
3