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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V216A is a family of low voltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.25µm CMOS technology.
The M5M5V216A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V216ATP (normal lead bend type package)
, M5M5V216ART (reverse lead bend type package) , both types
are very easy to design a printed circuit board.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,typ.)
No clocks, No refresh
Data retention supply voltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prevents data contention in the I/O bus
Process technology: 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Version,
Operating
temperature
Standard
0 ~ +70 C
Part name
M5M5V216ATP , RT -55L
M5M5V216ATP , RT -70L
M5M5V216ATP , RT -55H
M5M5V216ATP , RT -70H
Power
Supply
2.7 ~ 3.6V
2.7 ~ 3.6V
W-version
-20 ~ +85 C
M5M5V216ATP , RT -55LW
2.7 ~ 3.6V
M5M5V216ATP , RT -70LW
M5M5V216ATP , RT -55HW
M5M5V216ATP , RT -70HW 2.7 ~ 3.6V
I-version
-40 ~ +85 C
M5M5V216ATP , RT -55L I
M5M5V216ATP , RT -70L I
M5M5V216ATP , RT -55H I
M5M5V216ATP , RT -70H I
2.7 ~ 3.6V
2.7 ~ 3.6V
Access
time
max.
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
Stand-by current Icc(PD), Vcc=3.0V
typical *
Ratings (max.)
25 C 40 C 25 C 40 C 70 C 85 C
Active
current
Icc1
(3.0V, typ.)
--- --- --- --- 20µA ---
0.3µA 1µA 1µA 3µA 8µA ---
--- ---
45mA
--- --- 20µA 50µA (10MHz)
0.3µA 1µA 1µA 3µA 8µA 24µA 5mA
(1MHz)
--- ---
--- --- 20µA 50µA
0.3µA 1µA 1µA 3µA 8µA 24µA
PIN CONFIGURATION
* "typical" parameter is sampled, not 100% tested.
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
A5 44
43 A6
A6 43
42 A7
A7 42
41 OE
OE 41
40 BC2
BC2 40
39 BC1
BC1 39
38 DQ16 DQ16 38
37 DQ15 DQ15 37
36 DQ14 DQ14 36
35 DQ13 DQ13 35
34 GND
GND
34
33 Vcc
Vcc 33
32 DQ12 DQ12 32
31 DQ11 DQ11 31
30 DQ10 DQ10 30
29 DQ9
DQ9 29
28 NC
NC 28
27 A8
A8 27
26 A9
A9 26
25 A10
A10 25
24 A11
A11 24
23 NC
NC 23
1 A4
2 A3
3 A2
Pin
Function
4 A1
5 A0
A0 ~ A16 Address input
6
7
S DQ1 ~ DQ16 Data input / output
DQ1
8 DQ2
9 DQ3
10 DQ4
S Chip select input
W Write control input
11 Vcc
12 GND
OE Output inable input
13 DQ5
14 DQ6
15 DQ7
BC1
BC2
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
16 DQ8
17 WE
Vcc Power supply
18 A16
GND Ground supply
19 A15
20 A14
Outline: TP : 44P3W - H
21 A13
22 A12
RT : 44P3W - J
NC: No Connection
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by
16-bit. These devices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S. The address(A0~A16) must be set up before the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S are in
an active state(S=L).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selesctable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lower-
byte are in a selectable mode and upper-byte are in a
non-selectable mode.
BLOCK DIAGRAM
When setting BC1 and BC2 at a high level or S at a high
level, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply current is reduced as low as 0.3µA(25 C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S BC1 BC2 W OE Mode DQ1~8 DQ9~16 Icc
H X X X X Non selection High-Z High-Z Standby
L H H X X Non selection High-Z High-Z Standby
L L H L X Write Din High-Z Active
L L H H L Read Dout High-Z Active
L L H HH
High-Z High-Z Active
L H L L X Write High-Z Din Active
L H L H L Read High-Z Dout Active
L H L HH
High-Z High-Z Active
L L L L X Write Din Din Active
L L L H L Read Dout Dout Active
L L L HH
High-Z High-Z Active
A0
A1
MEMORY ARRAY
131072 WORDS
x 16 BITS
A15 -
A16
CLOCK
GENERATOR
S
DQ
1
DQ
8
DQ
9
DQ
16
BC1
BC2
W
OE
Vcc
GND
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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Units
Vcc Supply voltage
VI Input voltage
With respect to GND
With respect to GND
-0.5* ~ +4.6
-0.5* ~ Vcc + 0.5
V
VO Output voltage
With respect to GND
0 ~ Vcc
Pd Power dissipation
Operating
Ta
temperature
Tstg Storage temperature
Ta=25 C
Standard
W-version
I-version
700 mW
(-L, -H)
0 ~ +70
(-LW, -HW)
- 20 ~ +85
C
(-LI, -HI)
- 40 ~ +85
- 65 ~ +150
C
* -3.0V in case of AC (Pulse width <= 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min Typ Max
VIH High-level input voltage
2.0 Vcc+0.3V
VIL
VOH1
VOH2
VOL
II
IO
Icc1
Icc2
Icc3
Low-level input voltage
-0.3 *
High-level output voltage 1 IOH= -0.5mA
2.4
High-level output voltage 2 IOH= -0.05mA
Vcc-0.5V
Low-level output voltage IOL=2mA
Input leakage current
VI =0 ~ Vcc
Output leakage current
Active supply current
( AC,MOS level )
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2 <=0.2V , S <=0.2V
other inputs <= 0.2V or => Vcc-0.2V
Output - open (duty 100%)
f= 10MHz
f= 1MHz
-
-
Active supply current
( AC,TTL level )
Stand by supply current
( AC,MOS level )
BC1 and BC2=VIL , S=VIL
other pins =VIH or VIL
Output - open (duty 100%)
f= 10MHz
f= 1MHz
< 1 > -LW, -LI +70 ~ +85 C
S => Vcc - 0.2V,
other inputs = 0 ~ Vcc
-L, -LW, -LI
+70 C
-HW, -HI +70 ~ +85 C
< 2 > -H, -HW, -HI
BC1 and BC2 => Vcc - 0.2V
S <= 0.2V
-H
Other inputs=0~Vcc
-HW
+40 ~ +70 C
+25 ~ +40 C
0 ~ +25 C
- 20 ~ +25 C
-
-
-
-
-
-
-
-
-
-HI - 40 ~ +25 C -
45
5
45
5
-
-
-
-
1
0.3
0.3
0.3
0.6
0.4
±1
±1
60
15
60
15
60
25
30
10
5
2
2
2
Icc4 Stand by supply current
( AC,TTL level )
BC1 and BC2=VIH , S=VIL or S=VIH
Other inputs= 0 ~ Vcc
- - 0.5
Units
V
µA
mA
µA
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25 C
* -3.0V in case of AC (Pulse width <= 30ns)
CAPACITANCE
Symbol Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Min Typ Max
8
10
Units
pF
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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply voltage
Input pulse
Input rise time and fall time
Reference level
Output loads
2.7V~3.6V
VIH=2.2V,VIL=0.4V
5ns
VOH=VOL=1.5V
Transition is measured ±500mV from
steady state voltage.(for ten,tdis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
1TTL
DQ
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S high
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after OE high
Output enable time after S low
Output enable time after BC1 low
Output enable time after BC2 low
Output enable time after OE low
Data valid time after address
Limits
M5M5V216ATP,RT - 55
Min Max
M5M5V216ATP,RT - 70
Min Max
55 70
55 70
55 70
55 70
55 70
30 35
20 25
20 25
20 25
20 25
10 10
10 10
10 10
55
10 10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Limits
M5M5V216ATP,RT - 55 M5M5V216ATP,RT - 70
Min Max Min Max
55 70
45 55
00
50 65
50 65
50 65
50 65
25 30
00
00
20 25
20 25
55
55
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
(4)TIMING DIAGRAMS
Read cycle
A0~16
BC1
and / or
BC2
S
OE
W = "H" level
DQ1~16
(Note3)
(Note3)
(Note3)
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
tv (A)
ta(S)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S)
tdis (BC1) or tdis (BC1)
tdis (S)
tdis (OE)
VALID DATA
(Note3)
(Note3)
(Note3)
Write cycle ( W control mode )
tCW
A0~16
BC1
and / or
BC2
S
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S)
tsu (A-WH)
(Note3)
(Note3)
OE
W
DQ1~16
tsu (A)
tdis(OE)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
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