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revision-01, ' 98.12.08
M5M5V216AWG
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V216A is a family of low voltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.25µm CMOS technology.
The M5M5V216A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5V216AWG is packaged in a CSP (chip scale package),
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48pin)
and ball pitch of 0.75mm. It gives the best solution for a
compaction of mounting area as well as flexibility of wiring pattern
of printed circuit boards.
From the point of operating temperature, the family is divided
into three versions; "Standard", "W-version", and "I-version".
Those are summarized in the part name table below.
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,typ.)
No clocks, No refresh
Data retention supply voltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prevents data contention in the I/O bus
Process technology: 0.25µm CMOS
Package: 48 pin 7.0mm x8.5mm CSP
PART NAME TABLE
Version,
Operating
temperature
Part name
M5M5V216AWG -55L
Standard
0 ~ +70 C
M5M5V216AWG -70L
M5M5V216AWG -55H
M5M5V216AWG -70H
M5M5V216AWG -55LW
W-version
-20 ~ +85 C
M5M5V216AWG -70LW
M5M5V216AWG -55HW
M5M5V216AWG -70HW
M5M5V216AWG -55L I
I-version
-40 ~ +85 C
M5M5V216AWG -70L I
M5M5V216AWG -55H I
M5M5V216AWG -70H I
PIN CONFIGURATION
(TOP VIEW)
1 2 3456
A BC1 OE A6 A3 A0 NC
B
DQ
16
BC2
A7
A2
S
DQ
1
C
DQ DQ
14 15
A5
A1
DQ
2
DQ
3
D
GND
DQ
13
NC
A4
DQ
4
Vcc
E
Vcc
DQ
12
GND A16
DQ
5
GND
F
DQ DQ
11 10
A9
A14
DQ
7
DQ
6
G
DQ
9
NC
A10 A13
W
DQ
8
H NC A8 A11 A12 A15 NC
Power
Supply
Access
time
max.
Stand-by current Icc(PD), Vcc=3.0V
typical *
Ratings (max.)
25 C 40 C 25 C 40 C 70 C 85 C
Active
current
Icc1
(3.0V, typ.)
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V
70ns(@ 2.7V) / 65ns(@3.3V)
---
---
--- --- 20µA ---
2.7 ~ 3.6V
2.7 ~ 3.6V
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
0.3µA 1µA
--- ---
1µA
---
3µA 8µA ---
45mA
--- 20µA 50µA (10MHz)
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V 70ns(@ 2.7V) / 65ns(@3.3V) 0.3µA 1µA
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V
70ns(@ 2.7V) / 65ns(@3.3V)
---
---
1µA
---
3µA 8µA 24µA
--- 20µA 50µA
5mA
(1MHz)
55ns(@ 2.7V) / 50ns(@3.3V)
2.7 ~ 3.6V
0.3µA 1µA
70ns(@ 2.7V) / 65ns(@3.3V)
1µA
3µA 8µA 24µA
* "typical" parameter is sampled, not 100% tested.
(BOTTOM VIEW)
65 4321
A NC A0 A3 A6 OE BC1
B
DQ
1
S
A2
A7
BC2
DQ
16
C
DQ DQ
32
A1
A5
DQ
15
DQ
14
D
Vcc
DQ
4
A4
NC
DQ
13
GND
E
GND
DQ
5
A16 GND
DQ
12
Vcc
F
DQ
6
DQ
7
A14 A9
DQ
10
DQ
11
G
DQ
8
W
A13 A10 NC
DQ
9
H NC A15 A12 A11 A8 NC
Pin Function
A0 ~ A16 Address input
DQ1 ~ DQ16 Data input / output
S
W
OE
BC1
BC2
Vcc
Chip select input
Write control input
Output inable input
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
Power supply
GND Ground supply
Outline: 48FJA
NC: No Connection
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
M5M5V216AWG
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216AWG is organized as 131,072-words by
16-bit. These devices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S. The address(A0~A16) must be set up before the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S are in
an active state(S=L).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selesctable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lower-
byte are in a selectable mode and upper-byte are in a
non-selectable mode.
BLOCK DIAGRAM
When setting BC1 and BC2 at a high level or S at a high
level, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply current is reduced as low as 0.3µA(25 C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S BC1 BC2 W OE Mode DQ1~8 DQ9~16 Icc
H X X X X Non selection High-Z High-Z Standby
L H H X X Non selection High-Z High-Z Standby
L L H L X Write Din High-Z Active
L L H H L Read Dout High-Z Active
L L H HH
High-Z High-Z Active
L H L L X Write High-Z Din Active
L H L H L Read High-Z Dout Active
L H L HH
High-Z High-Z Active
L L L L X Write Din Din Active
L L L H L Read Dout Dout Active
L L L HH
High-Z High-Z Active
A0
A1
MEMORY ARRAY
131072 WORDS
x 16 BITS
A15 -
A16
CLOCK
GENERATOR
S
DQ
1
DQ
8
DQ
9
DQ
16
BC1
BC2
W
OE
Vcc
GND
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
M5M5V216AWG
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Units
Vcc Supply voltage
VI Input voltage
With respect to GND
With respect to GND
-0.5* ~ +4.6
-0.5* ~ Vcc + 0.5
V
VO Output voltage
With respect to GND
0 ~ Vcc
Pd Power dissipation
Operating
Ta
temperature
Tstg Storage temperature
Ta=25 C
Standard
W -version
I-version
700 mW
(-L, -H)
0 ~ +70
(-LW, -HW)
- 20 ~ +85
C
(-LI, -HI)
- 40 ~ +85
- 65 ~ +150
C
* -3.0V in case of AC (Pulse width <= 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min Typ Max
VIH High-level input voltage
2.0 Vcc+0.3V
VIL
VOH1
VOH2
VOL
II
IO
Icc1
Icc2
Icc3
Low-level input voltage
-0.3 *
High-level output voltage 1 IOH= -0.5mA
2.4
High-level output voltage 2 IOH= -0.05mA
Vcc-0.5V
Low-level output voltage IOL=2mA
Input leakage current
VI =0 ~ Vcc
Output leakage current
Active supply current
( AC,MOS level )
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2 <=0.2V , S <=0.2V
other inputs <= 0.2V or => Vcc-0.2V
Output - open (duty 100%)
f= 10MHz
f= 1MHz
-
-
Active supply current
( AC,TTL level )
Stand by supply current
( AC,MOS level )
BC1 and BC2=VIL , S=VIL
other pins =VIH or VIL
Output - open (duty 100%)
f= 10MHz
f= 1MHz
< 1 > -LW, -LI +70 ~ +85 C
S => Vcc - 0.2V,
other inputs = 0 ~ Vcc
-L, -LW, -LI
+70 C
-HW, -HI +70 ~ +85 C
< 2 > -H, -HW, -HI
BC1 and BC2 => Vcc - 0.2V
S <= 0.2V
-H
Other inputs=0~Vcc
-HW
+40 ~ +70 C
+25 ~ +40 C
0 ~ +25 C
- 20 ~ +25 C
-
-
-
-
-
-
-
-
-
-HI - 40 ~ +25 C -
45
5
45
5
-
-
-
-
1
0.3
0.3
0.3
0.6
0.4
±1
±1
60
15
60
15
60
20
30
10
5
2
2
2
Icc4 Stand by supply current
( AC,TTL level )
BC1 and BC2=VIH , S=VIL
Other inputs= 0 ~ Vcc
or S=VIH
- - 0.5
Units
V
µA
mA
µA
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25 C
* -3.0V in case of AC (Pulse width <= 30ns)
CAPACITANCE
Symbol Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Min Typ Max
8
10
Units
pF
MITSUBISHI ELECTRIC
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