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1997.01.22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V32R16 is a family of 32768-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by /LB
and /UB.
FEATURES
Fast access time M5M5V32R16J,TP-10 10ns(max)
M5M5V32R16J,TP-12 12ns(max)
M5M5V32R16J,TP-15 15ns(max)
Low power dissipation Active
297mW(typ)
Stand by
0.33mW(typ)
Single +3.3V power supply
Fully static operation : No clocks, No refresh
Common data I/O
Easy memory expansion by /S
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Directly TTL compatible : All inputs and outputs
Separate control of lower and upper bytes by /LB and /UB
PIN CONFIGURATION (TOP VIEW)
N.C
A3
ADDRESS
INPUTS
A2
A1
CHIP
SELECT
INPUTS
DATA
INPUTS/
OUTPUTS
A0
/S
DQ1
DQ2
DQ3
DQ4
(3.3V) Vcc
(0V) GND
DATA
INPUTS/
OUTPUTS
DQ5
DQ6
DQ7
WRITE
CONTROL
INPUT
DQ8
/W
A14
ADDRESS
INPUTS
A13
A12
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A4
43
A5
ADDRESS
INPUTS
42 A6
41
/OE
OUTPUT
ENABLE
40
/UB BYTE
CONTROL
39 /LB INPUTS
38 DQ16
35
DQ15
DATA
INPUTS/
36 DQ14 OUTPUTS
35 DQ13
34 GND (0V)
33 Vcc (3.3V)
32 DQ12
31
DQ11
DATA
INPUTS/
30 DQ10 OUTPUTS
29 DQ9
28 NC
27 A7
26 A8 ADDRESS
25 A9
INPUTS
24 A10
23 NC
Outline 44P0K(J)
44P3W-H(TP)
APPLICATION
High-speed memory system
FUNCTION
The operation mode of the M5M5V32R16 is
determined by a combination of the device control
inputs /S, /W, /OE, /LB, and /UB. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with low level /LB and/or low level /UB and low
level /S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
/W, /LB, /UB or /S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input /OE directly
controls the output stage. Setting the /OE at a high
level, the output stage is in a high impedance state, and
the data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and /OE at a low level while /LB and/or /UB and /S are
in an active state. (/LB and/or /UB=L, /S=L)
PACKAGE
M5M5V32R16J : 44pin 400mil SOJ
M5M5V32R16VP: 44pin 400mil TSOP(II)
When setting /LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting /UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and
upper-Byte are in a non-selectable mode.
When setting /LB and /UB at a high level or /S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by /LB, /UB and /S.
Signal-/S controls the power-down feature. When /S
goes high, power dissapation is reduced extremely.
The access time from /S is equivalent to the address
access time.
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION TABLE
/S /W /OE /LB /UB
Mode
LHL LL
Read cycle All Bytes
L H L H L Read cycle Upper Bytes
L H L L H Read cycle Lower Bytes
LLX LL
Write cycle All Bytes
L L X H L Write cycle Upper Bytes
L L X L H Write cycle Lower Bytes
L HH X X
L XX HH
HXX X X
Output disable
Non selection
DQ1 - 8
D OUT
High-impedance
D OUT
D IN
High-impedance
D IN
High-impedance
High-impedance
DQ9 - 16
D OUT
D OUT
High-impedance
D IN
D IN
High-impedance
High-impedance
High-impedance
Icc
Active
Active
Active
Active
Active
Active
Active
Stand by
BLOCK DIAGRAM
ADDRESS
INPUTS
A7 27
A6 42
A2 3
A1 4
A0 5
A14 18
A13 19
A12 20
A11 21
CHIP SELECT
INPUTS
/S 6
WRITE
CONTROL INPUT
/W 17
OUTPUT
ENABLE INPUT /OE 41
UPPER BYTE
CONTROL INPUTS /UB 40
LOWER BYTE
CONTROL INPUTS
/LB 39
MEMORY ARRAY
512 ROWS
1024 COLUMNS
COLUMN I/O CIRCUITS
COLUMN ADDRESS
DECODERS
COLUMN INPUT BUFFERS
24 25 26 43 44 2
A10 A9 A8 A5 A4 A3
ADDRESS INPUTS
MITSUBISHI
ELECTRIC
7 DQ1
8 DQ2
9 DQ3
10 DQ4
13 DQ5
14 DQ6
15 DQ7
16 DQ8
29 DQ9
30 DQ10
31 DQ11
32 DQ12
35 DQ13
36 DQ14
37 DQ15
38 DQ16
11 Vcc
33
12 GND
34
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MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vcc Supply voltage
-2.0* ~ 4.6
V
VI Input voltage
With respect to GND -2.0* ~ Vcc+0.5 V
VO Output voltage
-2.0* ~ Vcc
V
Pd Power dissipation
Ta=25 C
1000
mW
Topr
Operating temperature
0 ~ 70
C
Tstg(bias) Storage temperature(bias)
-10 ~ 85
C
Tstg Storage temperature
-65 ~ 150
C
* Pulse width <= 20ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V +-105%%, unless otherwise noted)
Symbol
Parameter
Condition
VIH
VIL
VOH
VOL
II
IOZ
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
Output current in off-state
IOH = - 4mA
IOL= 8mA
V I = 0 ~ Vcc
VI (/S)= VIH
VO= 0 ~ Vcc
Active supply current
I CC1 (TTL level)
VI (/S)= VIL
other inputs VIH or VIL
Output-open(duty 100%)
AC(10ns cycle)
AC(12ns cycle)
AC(15ns cycle)
DC
AC(10ns cycle)
I CC2
Stand-by supply current
(TTL level)
VI (/S)= VIH
AC(12ns cycle)
AC(15ns cycle)
I CC3
Stand-by current
(MOS level)
VI (/S)= Vcc=> 0.2V
other inputs VI <= 0.2V
or VI => Vcc - 0.2V
DC
* Pulse width <= 20ns, in case of AC : - 3.0V
CAPACITANCE (Ta=0 ~ 70 C, Vcc=3.3V+-105%% , unless otherwise noted)
Symbol
Parameter
Test Condition
C I Input capacitance
VI =GND,Vi =25mVrms,f=1MHz
CO Output capacitance
Vo =GND,Vo =25mVrms,f=1MHz
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc=3.3V,Ta=25 C
3: CI,CO are periodically sampled and are not 100% tested.
Min
2.0
-0.3*
2.4
Limits
Typ Max
Unit
Vcc+0.3 V
0.8 V
V
0.4 V
2 µA
10 µA
150
130 mA
110
90 100
60
55
50 mA
40
0.1 1 mA
Min
Limit
Typ Max
Unit
6 pF
8 pF
AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V +-105%%, unless otherwise noted)
(1) MEASUREMENT CONDITION
Input pulse levels
Input rise and fall time
Input timing reference levels
VIH =3.0V, V IL =0.0V
3ns
V IH =1.5V, VIL =1.5V
( )Including
scope and JIG
DQ
DQ
Vcc
480
Output timing reference levels
Output loads
V OH =1.5V, V OL =1.5V
Fig1,Fig2
50
VL=1.5V
2555pF
( )Including
scope and JIG
Fig.1 Output load
Fig.2 Output load for ten , tdis
MITSUBISHI
ELECTRIC
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