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revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V416B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V416BTP,RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V416BTP (normal lead bend ty pe package)
, M5M5V416BRT (rev erse lead bend ty pe package) , both ty pes
are v ery easy t o design a printed circuit board.
From the point of operating temperature, the f amily is div ided into
three v ersions; "Standard", "W-v ersion", and "I-v ersion". Those are
summarized in the part name table below.
Version,
Operating
Part name
temperature
M5M5V416BTP , RT -70L
M5M5V416BTP , RT -85L
Standard M5M5V416BTP , RT -10L
0 ~ +70°C M5M5V416BTP , RT -70H
M5M5V416BTP , RT -85H
M5M5V416BTP , RT -10H
M5M5V416BTP , RT -70LW
M5M5V416BTP , RT -85LW
W-v ersion M5M5V416BTP , RT -10LW
-20 ~ +85°C M5M5V416BTP , RT -70HW
M5M5V416BTP , RT -85HW
M5M5V416BTP , RT -10HW
M5M5V416BTP , RT -70LI
M5M5V416BTP , RT -85LI
I-v ersion M5M5V416BTP , RT -10LI
-40 ~ +85°C M5M5V416BTP , RT -70HI
M5M5V416BTP , RT -85HI
M5M5V416BTP , RT -10HI
PIN CONFIGURATION
Power
Supply
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
Access time
max.
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
Stand-by c urrent Icc(PD), Vcc=3.0V
Activ e
ty pical *
Ratings (max.)
current
Icc1
25°C 40°C 25°C 40°C 70°C 85°C (3.0V, ty p.)
--- --- --- --- 20µA ---
0.3µA 1µA 1µA 3µA 10µA ---
--- ---
0.3µA 1µA
--- ---
--- --- 20µA 40µA
1µA 3µA 10µA 20µA
--- --- 20µA 40µA
40mA
(10MHz)
5mA
(1MHz)
0.3µA 1µA 1µA 3µA 10µA 20µA
* "ty pical" parameter is sampled, not 100% tested.
A4
A3
A2
A1
A0
S1
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44P3W-H
44 A5
A5 44
43 A6
A6 43
42 A7
A7 42
41 OE
OE 41
40 BC2
BC2 40
39 BC1
BC1 39
38 DQ16 DQ16 38
37 DQ15 DQ15 37
36 DQ14 DQ14 36
35 DQ13 DQ13 35
34 GND
GND
34
33 Vcc
Vcc 33
32 DQ12 DQ12 32
31 DQ11 DQ11 31
30 DQ10 DQ10 30
29 DQ9
DQ9 29
28 S2
S2 28
27 A8
A8 27
26 A9
A9 26
25 A10
A10 25
24 A11
A11 24
23 A17
A17 23
1 A4
2 A3
3 A2
4 A1
Pin
Function
5 A0
6 S1
A0 ~ A17 Address input
7 DQ1 DQ1 ~ DQ16 Data input / output
8 DQ2
9 DQ3
S1 Chip select input 1
10 DQ4
11 Vcc
S2 Chip select input 2
12 GND
13 DQ5
14 DQ6
W Write control input
OE Output enable input
15 DQ7
16 DQ8
BC1
Lower By te (DQ1 ~ 8)
17 WE
18 A15
19 A14
BC2
Vcc
Upper By te (DQ9 ~ 16)
Power supply
20 A13
21 A12
GND
Ground supply
22 A16
Outline: 44P3W-H/J
44P3W-J
NC: No Connection
MITSUBISHI ELECTRIC
1

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revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V416BTP,RT are organized as 262,144-words
by 16-bit. These dev ices operate on a single +2.7~3.6V
power supply , and are directly TTL compatible to both
input and output. Its f ully static circuit needs no clocks
and no ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE.
Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W
ov erlaps with the low lev el BC1 and/or BC2 and the low
lev el S1 and the high lev el S2. The address(A0~A17) must
be set up bef ore the write cy cle and must be stable during
the entire cycle.
A read operation is executed by s etting W at a high lev el
and OE at a low lev el while BC1 and/or BC2 and S1 and
S2 are in an activ e state(S1=L,S2=H).
When setting BC1 at the high lev el and other pins are in
an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
BLOCK DIAGRAM
When setting BC1 and BC2 at a high lev el or S1 at a high
lev el or S2 at a low lev el, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1, BC2
and S1, S2.
The power supply c urrent is reduced as low as 0.3µA(25°C,
ty pical), and the memory data can be held at +2V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1 S2 BC1 BC2 W OE Mode DQ1~8 DQ9~16 Icc
H L X X X X Non selection High-Z High-Z Standby
L L X X X X Non selection High-Z High-Z Standby
H H X X X X Non selection High-Z High-Z Standby
X X H H X X Non selection High-Z High-Z Standby
L H L H L X Write Din High-Z Activ e
L H L H H L Read Dout High-Z Activ e
LH L H H H
High-Z High-Z Activ e
L H H L L X Write High-Z Din Activ e
L H H L H L Read High-Z Dout Activ e
LH H L H H
High-Z High-Z Activ e
L H L L L X Write Din Din Activ e
L H L L H L Read Dout Dout Activ e
LH L L H H
High-Z High-Z Activ e
A0
A1
MEMORY ARRAY
262144 WORDS
x 16 BITS
A16 -
A17
DQ
1
DQ
8
DQ
9
S1
CLOCK
GENERATOR
S2
DQ
16
BC1
BC2
Vcc
W
GND
OE
MITSUBISHI ELECTRIC
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revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Units
Vcc Supply v oltage
VI Input v oltage
With respect to GND
With respect to GND
-0.5* ~ +4.6
-0.5* ~ Vcc + 0.5
V
VO Output v oltage
With respect to GND
0 ~ Vcc
Pd Power dissipation
Ta=25°C
700 mW
Operating
Ta
temperature
Standard
W-v ersion
I-v ersion
(-L, -H)
(-LW, -HW)
(-LI, -HI)
0 ~ +70
- 20 ~ +85
- 40 ~ +85
°C
T stg Storage temperature
- 65 ~ +150
°C
* -3.0V in case of AC (Pulse width <= 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min Ty p Max Units
VIH High-lev el input v oltage
2.2 Vcc+0.3V
VIL
V OH1
V OH2
V OL
II
IO
Icc1
Icc2
Low-lev el input v oltage
High-level output voltage 1
IOH= -0.5mA
High-level output voltage 2
IOH= -0.05mA
Low-lev el output v oltage IOL=2mA
Input leakage current
VI =0 ~ Vcc
Output leakage current BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc
Activ e supply c urrent
( AC,MOS lev el )
BC1 and BC2<= 0.2V, S1<= 0.2V, S2 Vcc-0.2V
other inputs <= 0.2V or => Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Activ e supply c urrent
( AC,TTL lev el )
BC1 and BC2=VIL , S=V IL ,S2=V IH
other pins =V IH or VIL
Output - open (duty 100%)
f = 10MHz
f = 1MHz
-0.3 *
2.4
Vcc-0.5V
-
-
-
-
40
5
40
5
0.6
V
0.4
±1 µA
±1
50
10
mA
50
10
Icc3
Stand by s upply current
( AC,MOS lev el )
<1>
S1 => Vcc - 0.2V,
other inputs = 0 ~ Vcc
<2>
-LW, -LI
-L, -LW, -LI
-HW, -HI
S2 0.2V,
-H, -HW, -HI
other inputs = 0 ~ Vcc
<3>
BC1 and BC2 => Vcc - 0.2V
S1 <= 0.2V, S2 => Vcc - 0.2V
Other inputs=0~Vcc
-H
-HW
-HI
+70 ~ +85°C
+70°C
+70 ~ +85°C
+40 ~ +70°C
+25 ~ +40°C
0 ~ +25°C
- 20 ~ +25°C
- 40 ~ +25°C
-
-
-
-
-
-
-
-
- 48
- 24
- 24
- 12
µA
1 3.6
0.3 1.2
0.3 1.2
0.3 1.2
Icc4 Stand by s upply current BC1 and BC2=VIH or S1=VIH or S2=VIL
( AC,TTL lev el ) Other inputs= 0 ~ Vcc
- - 0.5 mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25°C
* -3.0V in case of AC (Pulse width <= 30ns)
CAPACITANCE
Symbol
Parameter
CI Input capacitance
CO Output capacitance
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Conditions
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
Limits
Min Ty p Max
10
10
Units
pF
MITSUBISHI ELECTRIC
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revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Supply v oltage
2.7V~3.6V
Input pulse
V IH= 2 . 4 V , V IL= 0 . 4 V
Input rise time and f all time 5ns
Ref erence lev el
Output loads
V OH=V OL= 1 . 5 V
Transition is measured ±500mV f rom
steady state voltage.(f or ten,t dis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
1TTL
DQ
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1 high
Output disable time af t er S2 low
Output disable time af t er BC1 high
Output disable time af t er BC2 high
Output disable time af t er OE high
Output enable time af ter S1 low
Output enable time af ter S2 high
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
70L,70H,70LW
70HW,70LI,70HI
Min Max
70
70
70
70
70
70
35
25
25
25
25
25
10
10
10
10
10
Limits
85L,85H,85LW
85HW,85LI,85HI
Min Max
85
85
85
85
85
85
45
30
30
30
30
30
10
10
10
10
5
10
10L,10H,10LW
10HW,10LI,10HI Units
Min Max
100 ns
100 ns
100 ns
100 ns
100 ns
100 ns
50 ns
35 ns
35 ns
35 ns
35 ns
35 ns
10 ns
10 ns
10 ns
10 ns
5 ns
10 ns
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
Write cy cle time
Write pulse width
tsu(A)
Address setup time
tsu(A-WH) Address setup time with respect to W
tsu(BC1) By te control 1 setup time
tsu(BC2) By te control 2 setup time
tsu(S1) Chip select 1 setup time
tsu(S2) Chip select 2 setup time
tsu(D)
Data setup time
th(D)
Data hold time
trec(W) Write recov ery time
tdis(W) Output disable time f rom W low
tdis(OE) Output disable time f rom OE high
ten(W) Output enable time f rom W high
ten(OE) Output enable time f rom OE low
Limits
70L,70H,70LW 85L,85H,85LW
70HW,70LI,70HI 85HW,85LI,85HI
Min Max Min Max
70 85
55 60
00
65 70
65 70
65 70
65 70
65 70
35 35
00
00
25
25
55
55
30
30
10L,10H,10LW
10HW,10LI,10HI
Min Max
100
75
0
85
85
85
85
85
40
0
0
35
35
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI ELECTRIC
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revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
(4)TIMING DIAGRAMS
Read cycle
A 0~17
BC1 ,BC2
S1
(Note3)
(Note3)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
tv (A)
ta(S1)
tdis (BC1) or tdis (BC1)
tdis (S1)
(Note3)
(Note3)
S2
(Note3)
OE
W = "H" lev el
(Note3)
DQ1~16
Write cycle ( W control mode )
ta(S2)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S1)
ten (S2)
tCW
tdis (S2)
tdis (OE)
VALID DATA
(Note3)
(Note3)
A 0~17
BC1,BC2
S1
S2
(Note3)
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S1)
tsu (S2)
(Note3)
(Note3)
(Note3)
OE
W
DQ1~16
tsu (A)
tdis(OE)
tsu (A-WH)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
MITSUBISHI ELECTRIC
5