M5M5V416BUG-70HI.pdf 데이터시트 (총 10 페이지) - 파일 다운로드 M5M5V416BUG-70HI 데이타시트 다운로드

No Preview Available !

revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V416B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V416BUG is packaged in a CSP (chip scale package),
with the outline of 7mm x 8.5mm, ball matrix of 6 x 8 (48pin) and
ball pitch of 0.75mm. It giv es the best solution f or a compaction
of mounting area as well as f lexibility of wiring pattern of printed
circuit boards.
Those are summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage =2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 48pin 7mm x 8.5mm CSP
Version,
Operating
temperature
Part name
I-v ersion
-40 ~ +85°C M5M5V416BUG -70HI
Power
Supply
2.7 ~ 3.6V
Access time
max.
Stand-by c urrent Icc(PD), Vcc=3.0V
Activ e
ty pical *
Ratings (max.)
current
Icc1
25°C 40°C 25°C 40°C 70°C 85°C (3.0V, ty p.)
70ns
0.3µA 1µA
1µA 3µA 15µA 30µA
50mA
(10MHz)
7mA
(1MHz)
* "ty pical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW)
1 23 4 56
A BC1 OE A0 A1 A2 S2
B DQ9 BC2 A3
A4 S1 DQ1
C DQ10 DQ11 A5
A6 DQ2 DQ3
D GND DQ12 A17 A7 DQ4 VCC
E VCC DQ13 GND A16 DQ5 GND
F DQ15 DQ14 A14 A15 DQ6 DQ7
G DQ16 N.C. A12 A13 W DQ8
H N.C. A8 A9 A10 A11 N.C.
Outline: 48FJA
NC: No Connection
Pin Function
A0 ~ A17 Address input
DQ1 ~ DQ16 Data input / output
S1 Chip select input 1
S2 Chip select input 2
W Write control input
OE
BC1
BC2
Vcc
Output enable input
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Power supply
GND Ground supply
MITSUBISHI ELECTRIC
1

No Preview Available !

revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V416BWG is organized as 262,144-words by
16-bit. These dev ices operate on a single +2.7~3.6V power
supply , and are directly TTL compatible to both input and
output. Its f ully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE.
Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W
ov erlaps with the low lev el BC1 and/or BC2 and the low
lev el S1 and the high lev el S2. The address(A0~A17) must
be set up bef ore the write cy cle and must be stable during
the entire cycle.
A read operation is executed by s etting W at a high lev el
and OE at a low lev el while BC1 and/or BC2 and S1 and
S2 are in an activ e state(S1=L,S2=H).
When setting BC1 at the high lev el and other pins are in
an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
BLOCK DIAGRAM
When setting BC1 and BC2 at a high lev el or S1 at a high
lev el or S2 at a low lev el, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1, BC2
and S1, S2.
The power supply c urrent is reduced as low as 0.3µA(25°C,
ty pical), and the memory data can be held at +2V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1 S2 BC1 BC2 W OE Mode DQ1~8 DQ9~16 Icc
H X X X X X Non selection High-Z High-Z Standby
X L X X X X Non selection High-Z High-Z Standby
X X H H X X Non selection High-Z High-Z Standby
L H L H L X Write Din High-Z Activ e
L H L H H L Read Dout High-Z Activ e
LH
LH
LH
L
H
H
H HH
L LX
L HL
Write
Read
High-Z High-Z Activ e
High-Z Din Activ e
High-Z Dout Activ e
LH
LH
LH
LH
H
L
L
L
L HH
L LX
L HL
L HH
Write
Read
High-Z High-Z
Din Din
Dout Dout
High-Z High-Z
Activ e
Activ e
Activ e
Activ e
A0
A1
MEMORY ARRAY
262144 WORDS
x 16 BITS
A16 -
A17
DQ
1
DQ
8
DQ
9
S1
CLOCK
GENERATOR
S2
DQ
16
BC1
BC2
Vcc
W
GND
OE
MITSUBISHI ELECTRIC
2

No Preview Available !

revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Vcc Supply v oltage
With respect to GND
VI Input v oltage
With respect to GND
VO Output v oltage
With respect to GND
Pd Power dissipation
Ta=25°C
Operating
T a I-v ersion
temperature
Ratings
-0.5* ~ +4.6
-0.5* ~ Vcc + 0.5
0 ~ Vcc
700
- 40 ~ +85
Units
V
mW
°C
T stg Storage temperature
- 65 ~ +150
°C
* -3.0V in case of AC (Pulse width <= 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Min Ty p Max Units
VIH
VIL
V OH1
V OH2
V OL
II
IO
Icc1
Icc2
Icc3
Icc4
High-lev el input v oltage
2.2
Low-lev el input v oltage
-0.3 *
High-level output voltage 1
High-level output voltage 2
IOH= -0.5mA
IOH= -0.05mA
2.4
Vcc-0.5V
Low-lev el output v oltage IOL=2mA
Input leakage current
VI =0 ~ Vcc
Output leakage current BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc
Activ e supply c urrent
( AC,MOS lev el )
BC1 and BC2<= 0.2V, S1<= 0.2V, S2 Vcc-0.2V
other inputs <= 0.2V or => Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
f = 1MHz
-
-
Activ e supply c urrent
( AC,TTL lev el )
BC1 and BC2=VIL , S=V IL ,S2=V IH
other pins =V IH or VIL
Output - open (duty 100%)
f = 10MHz
f = 1MHz
-
-
Stand by s upply current
( AC,MOS lev el )
<1>
S1 => Vcc - 0.2V,
other inputs = 0 ~ Vcc
<2>
S2 0.2V,
other inputs = 0 ~ Vcc
<3>
BC1 and BC2 => Vcc - 0.2V
S1 <= 0.2V, S2 => Vcc - 0.2V
Other inputs=0~Vcc
+85°C
+70°C
+40°C
0 ~ +25°C
- 20 ~ +25°C
- 40 ~ +25°C
-
-
-
-
-
-
Stand by s upply current BC1 and BC2=VIH or S1=VIH or S2=VIL
( AC,TTL lev el ) Other inputs= 0 ~ Vcc
-
Vcc+0.3V
0.6
V
0.4
±1 µA
±1
50 70
7 15
mA
50 70
7 15
- 40
- 20
1 5.0
µA
0.3 2.0
0.3 2.0
0.3 2.0
- 0.5 mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25°C
* -3.0V in case of AC (Pulse width <= 30ns)
CAPACITANCE
Symbol
Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Min Ty p Max
10
10
Units
pF
MITSUBISHI ELECTRIC
3

No Preview Available !

revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Supply v oltage
2.7V~3.6V
Input pulse
V IH= 2 . 4 V , V IL= 0 . 4 V
Input rise time and f all time 5ns
Ref erence lev el
Output loads
V OH=V OL= 1 . 5 V
Transition is measured ±500mV f rom
steady state voltage.(f or ten,t dis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
(2) READ CYCLE
1TTL
DQ
CL
Including scope and
jig capacitance
Fig.1 Output load
Symbol
Parameter
t CR
ta(A)
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1 high
Output disable time af t er S2 low
Output disable time af t er BC1 high
Output disable time af t er BC2 high
Output disable time af t er OE high
Output enable time af ter S1 low
Output enable time af ter S2 high
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
(3) WRITE CYCLE
Limits
Min Max
70
70
70
70
70
70
35
25
25
25
25
25
10
10
10
10
5
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Parameter
tCW Write cy cle time
tw(W) Write pulse width
tsu(A) Address setup time
tsu(A-WH) Address setup time with respect to W
tsu(BC1) By te control 1 setup time
tsu(BC2) By te control 2 setup time
tsu(S1) Chip select 1 setup time
tsu(S2) Chip select 2 setup time
tsu(D) Data setup time
th(D)
Data hold time
trec(W) Write recov ery time
tdis(W) Output disable time f rom W low
tdis(OE) Output disable time f rom OE high
ten(W) Output enable time f rom W high
ten(OE) Output enable time f rom OE low
Limits
Min Max
70
55
0
60
60
60
60
60
35
0
0
25
25
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI ELECTRIC
4

No Preview Available !

revision-01, 17th July '00
M5M5V416BUG - 70H I
MITSUBISHI LSIs
(4)TIMING DIAGRAMS
Read cycle
A 0~17
BC1 ,BC2
S1
(Note3)
(Note3)
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
tv (A)
ta(S1)
tdis (BC1) or tdis (BC1)
tdis (S1)
(Note3)
(Note3)
S2
(Note3)
OE
W = "H" lev el
(Note3)
DQ1~16
Write cycle ( W control mode )
ta(S2)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S1)
ten (S2)
tCW
tdis (S2)
tdis (OE)
VALID DATA
(Note3)
(Note3)
A 0~17
BC1,BC2
S1
S2
(Note3)
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S1)
tsu (S2)
(Note3)
(Note3)
(Note3)
OE
W
DQ1~16
tsu (A)
tdis(OE)
tsu (A-WH)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
MITSUBISHI ELECTRIC
5