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2003.08.21 Ver. 7.0
www.DataSheet4U.com
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V416CWG is a f amily of low v oltage 4-Mbit static RAMs - Single 2.7~3.6V power supply
organized as 262144-words by 16-bit, f abricated by Renesas's - Small stand-by current: 0.2µA (3.00V, ty p.)
high-perf ormance 0.18µm CMOS technology .
- No clocks, No ref resh
The M5M5V416C is suitable f or memory applications where a
- Data retention supply v oltage =2.0V
simple interf acing , battery operating and battery backup are the - All inputs and outputs are TTL compatible.
important design objectiv es.
- Easy memory expansion by S1#, S2, BC1# and BC2#
M5M5V416CWG is packaged in a CSP (chip scale package),
- Common Data I/O
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) - Three-state outputs: OR-tie capability
and ball pitch of 0.75mm. It giv es the best solution f or
- OE# prev ents data contention in the I/O bus
a compaction of m ounting area as well as f lexibility of wiring
- Process technology : 0.18µm CMOS
pattern of printed circuit boards.
- Package: 48ball 7.0mm x 8.5mm CSP
Version,
Operating
temperature
Part name
I-version
-40 ~ +85°C
M5M5V416CWG -55HI
M5M5V416CWG -70HI
Power
Supply
Access time
max.
Stand-by c urrent (µA)
* Typical(3.0V)
Ratings (max. @3.6V)
25°C 40°C Voltage 25°C 40°C 70°C 85°C
Activ e
current
Icc1
(3.0V, ty p.)
2.7 ~ 3.6V
55ns
70ns
3.0V 1.0 2.0 10 20
30mA
0.2 0.4 3.3V 1.5 2.5 10
20
(10MHz)
5mA
3.6V 2.5 4.0 10 20 (1MHz)
PIN CONFIGURATION
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
(TOP VIEW)
1 23 456
A BC1# OE#
A0
A1
A2 S2
B DQ16 BC2#
A3
A4 S1# DQ1
C DQ14 DQ15
A5
A6 DQ2 DQ3
D GND DQ13
A17
A7 DQ4 VCC
E VCC
DQ12
NC or
GND
A16
DQ5 GND
F DQ11 DQ10 A14 A15 DQ7 DQ6
G DQ9
N.C. A12
A13 W#
DQ8
H N C A8 A9 A10 A11 N.C.
Outline: 48FJA
NC: No Connection
*Don't connect E3 ball to voltage level more than 0V.
Pin Function
A0 ~ A17 Address input
DQ1 ~ DQ16 Data input / output
S1# Chip select input 1
S2 Chip select input 2
W# Write control input
OE#
BC1#
Output enable input
Lower By te (DQ1 ~ 8)
BC2# Upper By te (DQ9 ~ 16)
Vcc Power supply
GND
Ground supply
1

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2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V416CWG is organized as 262144-words by
16-bit. These dev ices operate on a single +2.7~3.6V power
supply , and are directly TTL compatible to both input and
output. Its f ully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and
OE#. Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address(A0~A17)
must be set up bef ore the write cy c le and must be stable
during the entire cy c le.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S1# and S2 are in an activ e state(S1#=L,S2=H).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
BLOCK DIAGRAM
When setting BC1# and BC2# at a high lev el or S1# at a
high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by BC1#, BC2# and S1#, S2.
The power supply c urrent is reduced as low as 0.2µA(25°C,
ty pical), and the memory data can be held at +2V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1# S2 BC1# BC2# W# OE# Mode DQ1~8 DQ9~16 Icc
X L X X X X Non selection High-Z High-Z Standby
H H X X X X Non selection High-Z High-Z Standby
X X H H X X Non selection High-Z High-Z Standby
L H L H L X Write Din High-Z Activ e
L H L H H L Read Dout High-Z Activ e
LH L HH H
High-Z High-Z Activ e
L H H L L X Write High-Z Din Activ e
L H H L H L Read High-Z Dout Activ e
LH H L HH
High-Z High-Z Activ e
L H L L L X Write Din Din Activ e
L H L L H L Read Dout Dout Activ e
LH L L HH
High-Z High-Z Activ e
(note) "H" and "L" in this table mean VIH and VIL, respectiv ely .
"X" in this table should be "H" or "L".
A0
A1
MEMORY ARRAY
262144 WORDS
x 16 BITS
A16 -
A17
DQ
1
DQ
8
DQ
9
S1#
S2
CLOCK
GENERATOR
DQ
16
BC1#
BC2#
Vcc
W#
OE#
GND
2

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2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply v oltage
VI Input v oltage
VO Output v oltage
Pd Power dissipation
Operating
T a temperature
T stg Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
I-v ersion
Ratings
-0.5* ~ +4.6
-0.3* ~ Vcc + 0.3
0 ~ Vcc
700
- 40 ~ +85
Units
V
mW
°C
- 65 ~ +150
* -3.0V in case of AC (Pulse width < 30ns)
°C
DC ELECTRICAL CHARACTERISTICS
( Vcc=2.7 ~ 3.6V, unless noted. )
Symbol
Parameter
Conditions
VIH High-lev el input v oltage
VIL Low-lev el input v oltage
VOH High-level output voltage
IOH= -0.5mA
VOL Low-lev el output v oltage IOL=2mA
II Input leakage current
VI=0 ~ Vcc
IO Output leakage current BC1#andBC2#=VIH or S1#=VIH or S2=VILorOE#=VIH,VI/O=0~Vcc
Icc1 Activ e supply c urrent
( AC,MOS lev el )
BC1# and BC2#< 0.2V,S1#< 0.2V,S2>Vcc-0.2V
other inputs < 0.2V or > Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Activ e supply c urrent
Icc2
( AC,TTL lev el )
BC1# and BC2# =V IL , S1# =V IL ,S2=V IH
other pins =V IH or VIL
Output - open (duty 100%)
f = 10MHz
f = 1MHz
3.0V
Icc3 Stand by s upply current
( MOS lev el )
(1) S1# > Vcc - 0.2V,
S2 > Vcc - 0.2V,
other inputs = 0 ~ Vcc
(2) S2 <0.2V,
other inputs = 0 ~ Vcc
(3) BC1# and BC2#>Vcc-0.2V
S1# < 0.2V,S2> Vcc - 0.2V
other inputs = 0 ~ Vcc
~ +25°C
~ +40°C
~ +70°C
3.3V
3.6V
3.0V
3.3V
3.6V
3.0V~3.6V
Min
2.2
-0.2 *
2.4
-
-
-
-
-
-
-
Limits
Ty p Max Units
Vcc+0.2V
0.4 V
0.4
±1
±1
30 50
5 10
30 50
5 10
1.0
0.2 1.5
2.5
2.0
0.4 2.5
4.0
- 10
µA
mA
µA
Icc4
Stand by s upply current
( TTL lev el )
~ +85°C
BC1# and BC2# =VIH or S1# =VIH or S2=VIL
Other inputs= 0 ~ Vcc
3.0V~3.6V
-
-
- 20
- 2 mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
* -1.0V in case of AC (Pulse width < 30ns)
Note 2: Typical parameter indicates the value for the center of distribution at 3.00V, and is not 100% tested.
CAPACITANCE
Symbol Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
(Vcc=2.7 ~ 3.6V, unless noted. )
Limits
Min Ty p Max
10
10
Units
pF
3

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2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless noted. )
(1) TEST CONDITIONS
Supply v oltage
2.7~3.6V
Input pulse
VIH=2.4V, VIL=0.2V
Input rise time and f all time 5ns
Ref erence lev el
V OH=V OL= 1 . 5 0 V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
DQ
1TTL
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1# high
Output disable time af t er S2 low
Output disable time af t er BC1# high
Output disable time af t er BC2# high
Output disable time af t er OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time after address
(3) WRITE CYCLE
Symbol
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
Limits
5 5 HI
Min Max
55
55
55
55
55
55
30
20
20
20
20
20
10
10
5
5
5
10
Limits
70HI
Min Max
70
70
70
70
70
70
35
25
25
25
25
25
10
10
5
5
5
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
5 5 HI
Min Max
55
45
0
50
50
50
50
50
30
0
0
20
20
5
5
Limits
70HI
Min Max
70
55
0
60
60
60
60
60
35
0
0
25
25
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4

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2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A 0~17
ta(A)
tv (A)
BC1#,BC2#
(Note3)
ta(BC1) or ta(BC2)
tdis (BC1) or tdis (BC1)
(Note3)
S1#
(Note3)
ta(S1)
tdis (S1)
(Note3)
S2
(Note3)
OE#
W# = "H" lev el
(Note3)
DQ1~16
Write cycle (W# control mode )
ta(S2)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S1)
ten (S2)
tCW
tdis (S2)
tdis (OE)
VALID DATA
(Note3)
(Note3)
A 0~17
BC1#,BC2#
S1#
S2
(Note3)
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S1)
tsu (S2)
(Note3)
(Note3)
(Note3)
OE#
W#
DQ1~16
tsu (A)
tsu (A-WH)
tw (W)
tdis (W)
tdis(OE)
DATAIN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
5