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MITSUBISHI LSIs
M5M5V4R04J-12,-15
1997.11.20 Rev.F
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V4R04J is a family of 1048576-word by 4-bit static PIN CONFIGURATION (TOP VIEW)
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
The M5M5V4R04J is offered in a 32-pin plastic small outline J-
lead package(SOJ).
These device operate on a single 3.3V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M5V4R04J-12 •••• 12ns(max)
M5M5V4R04J-15 •••• 15ns(max)
• Low power dissipation Active •••••••••• 297mW(typ)
Stand by ••••••• 3.3mW(typ)
• Single +3.3V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
A0 1
address
inputs
A1 2
A2 3
A3 4
chip select A4 5
input
S6
data inputs/
outputs(3.3V)
DQ1
VCC
7
8
(0V) GND 9
data inputs/
outputs
DQ2 10
write control W 11
input
A5 12
address
inputs
A6 13
A7 14
A8 15
A9 16
Outline
32 A19
31 A18
30 A17
29 A16
address
inputs
28 A15
27 OE
output enable
input
26 DQ4 data inputs/
25 GND (0V) outputs
24 VCC (3.3V)
23 DQ3
22 A14
data inputs/
outputs
21 A13
20 A12
19 A11
18 A10
address
inputs
17 NC
32P0K(SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
address
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 12
A6 13
A7 14
A8 15
S6
W 11
OE 27
PACKAGE
32pin 400mil SOJ
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN I/O CIRCUITS
COLCUOMLUNMN ADDRESS
ADDREDSESCODERS
DECODERS
COLUMN INPUT BUFFERS
16 18 19 20 21 22 28 29 30 31 32
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
address
inputs
MITSUBISHI
ELECTRIC
7 DQ1
10 DQ2
23 DQ3
26 DQ4
data
inputs/
outputs
8
VCC (3.3V)
24
9
GND (0V)
25
1

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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V4R04J is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus
FUNCTION TABLE
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-
selectable mode in which both reading and writing are
disable. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
S W OE
HXX
LLX
L HL
L HH
Mode
Non selection
Write
Read
DQ
High-impedance
Din
Dout
High-impedance
Icc
Stand by
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V cc Supply voltage
Conditions
Ratings
-2.0* ~ 4.6
Unit
V
VI Input voltage
VO Output voltage
With respect to GND
-2.0* ~ VCC+0.5
-2.0* ~ VCC+0.5
V
V
Pd Power dissipation
Ta=25 C
1000
mW
T opr
Operating temperature
Tstg(bias) Storage temperature (bias)
Tstg Storage temperature
0 ~ 70
-10 ~ 85
-65 ~ 150
C
C
C
*Pulse width 20ns, In case of DC:-0.5V
DC
ELECTRICAL
CHARACTERISTICS (Ta=0
~
70
C,
Vcc=3.3V
+10%
-5%
unless
otherwise
noted)
Symbol
Parameter
Condition
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage IOH =-4mA
VOL Low-level output voltage IOL= 8mA
I I Input current
V I = 0~Vcc
I OZ
Output current in off-state
VI (S)= VIH
VO= 0~Vcc
I CC1
Active supply current
(TTL level)
VI (S)= VIL
other inputs V IH or VIL
Output-open(duty 100%)
Stand by current
I CC2 (TTL level)
VI (S)= VIH
Limits
Min Typ Max
Unit
2.0 Vcc+0.3 V
-0.3 0.8 V
2.4 V
0.4 V
2 µA
10 µA
12ns cycle
AC
15ns cycle
DC
12ns cycle
AC 15ns cycle
DC
160
150 mA
90 100
75
70 mA
50
I CC3 Stand by current
VI (S)= Vcc0.2V
other inputs VI0.2V
or VIVcc-0.2V
1 10 mA
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
CAPACITANCE
(Ta=0 ~ 70 C, Vcc=3.3V
+10%
-5% unless otherwise noted)
Symbol
Parameter
Test Condition
CI Input capacitance
V I =GND, V I =25mVrms,f=1MHz
CO Output capacitance
V O=GND, VO=25mVrms,f=1MHz
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc=5V,Ta=25 C
3: CI,CO are periodically sampled and are not 100% tested.
Limit
Min
Typ
Unit
Max
7 pF
8 pF
AC
ELECTRICAL
CHARACTERISTICS
(Ta=0 ~ 70 C, Vcc=3.3V
+10%
-5% unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels •••••••••••••••••••••••• V IH =3.0V, V IL =0.0V
Input rise and fall time •••••••••••••••••••••••••••••••••••••• 3ns
Input timing reference levels •••••••••••• V IH=1.5V, V IL=1.5V
Output timing reference levels •••••••••• V OH=1.5V, V OL =1.5V
Output loads •••••••••••••••••••••••••••••••••••••••••• Fig1 ,Fig2
OUTPUT Z0=50
RL=50
VL=1.5V
Fig.1 Output load
Vcc
480
DQ 5pF
255
(including
scope and JIG)
Fig.2 Output load for t en, t dis
MITSUBISHI
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(2)READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis (OE)
ten(S)
ten (OE)
tv(A)
tPU
tPD
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address change
Power-up time after chip selection
Power-down time after chip selection
MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
Limits
M5M5V4R04J -12 M5M5V4R04J -15
Min Max Min Max
Unit
12 15 ns
12 15 ns
12 15 ns
6 8 ns
0 6 0 7 ns
0 6 0 7 ns
0 0 ns
0 0 ns
3 3 ns
0
12
0 ns
15 ns
(3)WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
Write cycle time
Write pulse width
tsu(A)1 Address setup time(W)
tsu(A)2 Address setup time(S)
tsu (S)
Chip select setup time
tsu (D)
Data setup time
th(D)
Data hold time
trec(W) Write recovery time
tdis (W) Output disable time after W low
tdis (OE) Output disable time after OE high
ten (W) Output enable time after W high
ten (OE) Output enable time after OE low
tsu(A-WH) Address to W High
Limits
M5M5V4R04J -12 M5M5V4R04J -15
Unit
Min Max Min Max
12 15 ns
10 12 ns
0 0 ns
0 0 ns
10 12 ns
6 7 ns
0 0 ns
1 1 ns
0 6 0 7 ns
0 6 0 7 ns
0 0 ns
0 0 ns
10 12 ns
MITSUBISHI
ELECTRIC
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MITSUBISHI LSIs
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~19
VIH
VIL
DQ1~4
VOH
VOL
tv (A)
PREVIOUS DATA VALID
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv (A)
DATA VALID
Read cycle 2 (Note 4)
VIH
S VIL
t CR
ta(S)
(Note 5)
ten (S)
(Note 5)
tdis(S)
DQ1~4
VOH
VOL
ICC1
Icc
ICC2
W=H
OE=L
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
Note 4. Addresses valid prior to or coincident with S transition low.
5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6)
VIH
OE VIL
t CR
ta (OE)
(Note 5)
tdis(OE)
(Note 5) ten(OE)
DQ1~4
VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
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