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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
MITSUBISHI LSIs
M5M5V4R08J-12,-15,-20
1997.02.06 Rev.D
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V4R08J is a family of 524288-word by 8-bit static PIN CONFIGURATION (TOP VIEW)
RAMs, fabricated with the high performance CMOS silicon
gate process and designed for high speed application.
The M5M5V4R08J is offered in a 36-pin plastic small outline
J-lead package(SOJ).
These device operate on a single 3.3V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M5V4R08J-12 •••• 12ns(max)
M5M5V4R08J-15 •••• 15ns(max)
M5M5V4R08J-20 •••• 20ns(max)
• Low power dissipation Active •••••••••• 363mW(typ)
Stand by ••••••• 3.3mW(typ)
• Single +3.3V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
A0 1
address
inputs
chip select
input
data inputs/
outputs
A1
A2
A3
A4
S
DQ1
DQ2
2
3
4
5
6
7
8
(3.3V) VCC 9
(0V)
data
inputs/
GND
DQ3
10
11
outputs DQ4 12
write control
input
W 13
A5 14
address
inputs
A6 15
A7 16
A8 17
A9 18
Outline
36 NC
35 A18
34 A17
33 A16
address
inputs
32 A15 output enable
31 OE input
30 DQ8
29 DQ7
data
inputs/
outputs
28 GND(0V)
27 VCC (3.3V)
26 DQ6
25 DQ5
data
inputs/
outputs
24 A14
23 A13
22 A12
21 A11
address
inputs
20 A10
19 NC
36P0K (SOJ)
APPLICATION
High-speed memory units
BLOCK DIAGRAM
PACKAGE
36pin 400mil SOJ
address
inputs
A0 1
A1 2
A2 3
A3 4
A4 5
A5 14
A6 15
A7 16
A8 17
S6
W 13
OE 31
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN I/O CIRCUITS
CCOOLLUUMMNNADDRESS
ADDDREECSOSDERS
DECODERS
COLUMN INPUT BUFFERS
7 DQ1
8 DQ2
11 DQ3
12 DQ4
25 DQ5
26 DQ6
29 DQ7
30 DQ8
data
inputs/
outputs
9 VCC (3.3V)
27
10
GND (0V)
28
18 20 21 22 23 24 32 33 34 35
A9 A10 A11A12 A13 A14 A15 A16 A16 A17
address inputs
MITSUBISHI
ELECTRIC
1

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MITSUBISHI LSIs
M5M5V4R08J-12,-15,-20
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V4R08J is determined by a
combination of the device control inputs S, W and OE. Each mode
is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the write
cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high impedance state, and the data bus
FUNCTION TABLE
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and OE at a
low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-selectable
mode in which both reading and writing are disable. In this mode,
the output stage is in a high-impedance state, allowing OR-tie
with other chips and memory expansion by S.
Signal-S controls the power-down feature. When S goes high,
power dissapation is reduced extremely. The access time from S is
equivalent to the address access time.
S W OE
HXX
LLX
L HL
L HH
Mode
Non selection
Write
Read
DQ
High-impedance
Din
Dout
High-impedance
Icc
Stand by
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V cc Supply voltage
Conditions
Ratings
-2.0* ~ 4.6
Unit
V
VI Input voltage
VO Output voltage
With respect to GND
-2.0* ~ VCC+0.5
-2.0 * ~ VCC+0.5
V
V
Pd Power dissipation
Ta=25 C
1000
mW
Topr
Operating temperature
0 ~ 70
C
Tstg(bias) Storage temperature(bias)
-10 ~ 85
C
Tstg Storage temperature
-65 ~ 150
C
*Pulse width 20ns, In case of DC:-0.5V
DC
ELECTRICAL
CHARACTERISTICS (Ta=0
~
70
C,
Vcc=3.3V
+10%
-5%
unless
otherwise
noted)
Symbol
Parameter
Condition
Limits
Min Typ Max
Unit
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage IOH =-4mA
VOL Low-level output voltage IOL= 8mA
I I Input current
V I = 0~Vcc
I OZ
Output current in off-state VI (S)= VIH
VO= 0~Vcc
Active supply current
I CC1 (TTL level)
VI (S)= VIL
other inputs VIH or VIL
Output-open(duty 100%)
Stand by current
I CC2 (TTL level)
VI (S)= VIH
I CC3 Stand by current
*Pulse width 20ns, in case of AC :-3.0V
VI (S)= Vcc0.2V
other inputs VI0.2V
or VIVcc-0.2V
2.0
-0.3*
2.4
12ns cycle
AC 15ns cycle
20ns cycle
DC
12ns cycle
AC 15ns cycle
20ns cycle
DC
Vcc+0.3
0.8
0.4
2
V
V
V
V
µA
10 µA
170
160 mA
150
110 120
85
80 mA
75
60
1 10 mA
MITSUBISHI
ELECTRIC
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