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2001.July Rev.0.1
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V
I/O supply or a single 3.3V power supply and are 3.3V CMOS
compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz
• Fast access time: 3.8 ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need to
control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all
Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous self-
timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
100pin TQFP
PART NAME TABLE
Part Name
Frequency
M5M5V5636GP - 16 167MHz
Access
3.8ns
Cycle
6.0ns
Active Current
(max.)
340mA
Standby Current
(max.)
20mA
1
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PIN CONFIGURATION(TOP VIEW)
100pin TQFP
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
A9 81
A8 82
A17 83
A18 84
ADV 85
G# 86
CKE# 87
W# 88
CLK 89
VSS 90
VDD 91
E3# 92
BWa# 93
BWb# 94
BWc# 95
BWd# 96
E2 97
E1# 98
A7 99
A6 100
M5M5V5636GP
50 A10
49 A11
48 A12
47 A13
46 A14
45 A15
44 A16
43 NC
42 NC
41 VDD
40 VSS
39 NC
38 NC
37 A0
36 A1
35 A2
34 A3
33 A4
32 A5
31 LBO#
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
2
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BLOCK DIAGRAM
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
VDD
VDDQ
A0
A1
A2~18
19
LBO#
CLK
CKE#
ZZ
ADV
BWa#
BWb#
BWc#
BWd#
W#
G#
E1#
E2
E3#
ADDRESS
REGISTER
19 17
A1
D1
A0
D0
LINEAR/
INTERLEAVED
BURST
COUNTER
A1'
Q1
A0'
Q0
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
19
19
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
READ
LOGIC
BYTE1
WRITE
DRIVERS
BYTE2
WRITE
DRIVERS
BYTE3
WRITE
DRIVERS
BYTE4
WRITE
DRIVERS
36
256Kx36
MEMORY
ARRAY
INPUT
REGISTER1
INPUT
REGISTER0
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
3
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M5M5V5636GP REV.0.1