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2001.July Rev.0.1
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Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V
I/O supply or a single 3.3V power supply and are 3.3V CMOS
compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 167 MHz
• Fast access time: 3.8 ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need to
control G#
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• Three chip enables for simple depth expansion
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all
Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous self-
timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
Package
100pin TQFP
PART NAME TABLE
Part Name
Frequency
M5M5V5636GP - 16 167MHz
Access
3.8ns
Cycle
6.0ns
Active Current
(max.)
340mA
Standby Current
(max.)
20mA
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PIN CONFIGURATION(TOP VIEW)
100pin TQFP
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
A9 81
A8 82
A17 83
A18 84
ADV 85
G# 86
CKE# 87
W# 88
CLK 89
VSS 90
VDD 91
E3# 92
BWa# 93
BWb# 94
BWc# 95
BWd# 96
E2 97
E1# 98
A7 99
A6 100
M5M5V5636GP
50 A10
49 A11
48 A12
47 A13
46 A14
45 A15
44 A16
43 NC
42 NC
41 VDD
40 VSS
39 NC
38 NC
37 A0
36 A1
35 A2
34 A3
33 A4
32 A5
31 LBO#
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
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BLOCK DIAGRAM
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
VDD
VDDQ
A0
A1
A2~18
19
LBO#
CLK
CKE#
ZZ
ADV
BWa#
BWb#
BWc#
BWd#
W#
G#
E1#
E2
E3#
ADDRESS
REGISTER
19 17
A1
D1
A0
D0
LINEAR/
INTERLEAVED
BURST
COUNTER
A1'
Q1
A0'
Q0
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
19
19
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
READ
LOGIC
BYTE1
WRITE
DRIVERS
BYTE2
WRITE
DRIVERS
BYTE3
WRITE
DRIVERS
BYTE4
WRITE
DRIVERS
36
256Kx36
MEMORY
ARRAY
INPUT
REGISTER1
INPUT
REGISTER0
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
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MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION
Pin
A0~A18
BWa#, BWb#,
BWc#, BWd#
CLK
E1#
Name
Synchronous
Address
Inputs
Synchronous
Byte Write
Enables
Clock Input
Synchronous
Chip Enable
Function
These inputs are registered and must meet the setup and hold times around the rising edge of CLK.
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst
counter if burst is desired.
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls
DQc, DQPc pins; BWd# controls DQd, DQPd pins.
This signal registers the address, data, chip enables, byte write enables
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock's rising edge.
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
E2
Synchronous
Chip Enable
This active High input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
E3#
G#
ADV
CKE#
ZZ
W#
Synchronous
Chip Enable
Output Enable
Synchronous
Address
Advance/Load
Synchronous
Clock Enable
Snooze
Enable
Synchronous
Read/Write
This active Low input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
This active LOW asynchronous input enable the data I/O output drivers.
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
This active LOW input permits CLK to propagate throughout the device. When HIGH, the device
ignores the CLK input and effectively internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
This active HIGH asynchronous input causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active, all other inputs are ignored. When this
pin is LOW or NC, the SRAM normally operates.
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
DQa,DQPa,DQb,DQPb
DQc,DQPc,DQd,DQPd
LBO#
VDD
VSS
VDDQ
VSSQ
MCH
NC
Synchronous
Data I/O
Burst Mode
Control
VDD
VSS
VDDQ
VSSQ
Must Connect High
No Connect
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
Core Power Supply
Core Ground
I/O buffer Power supply
I/O buffer Ground
These pins should be connected to HIGH
These pins are not internally connected and may be connected to ground.
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MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
Operation
LBO#
HIGH or NC
LOW
Interleaved Burst Sequence
Linear Burst Sequence
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A18~A2
First access, latch external address
A18~A2
Second access(first burst address)
latched A18~A2
Third access(second burst address)
latched A18~A2
Fourth access(third burst address)
latched A18~A2
A1,A0
0,0 0,1 1,0 1,1
0,1 0,0 1,1 1,0
1,0 1,1 0,0 0,1
1,1 1,0 0,1 0,0
Linear Burst Sequence (when LBO# = LOW)
Operation
A18~A2
First access, latch external address
A18~A2
Second access(first burst address)
latched A18~A2
Third access(second burst address)
latched A18~A2
Fourth access(third burst address)
latched A18~A2
Note7. The burst sequence wraps around to its initial state upon completion.
A1,A0
0,0 0,1 1,0 1,1
0,1 1,0 1,1 0,0
1,0 1,1 0,0 0,1
1,1 0,0 0,1 1,0
TRUTH TABLE
Address
E1# E2 E3# ZZ
ADV W# BWx#
G# CKE# CLK
DQ
used
Operation
H X X L L X X X L L->H High-Z None Deselect Cycle
X L X L L X X X L L->H High-Z None Deselect Cycle
X X H L L X X X L L->H High-Z None Deselect Cycle
X X X L H X X X L L->H High-Z None Continue Deselect Cycle
L H L L L H X L L L->H Q External Read Cycle, Begin Burst
X X X L H X X L L L->H Q Next Read Cycle, Continue Burst
L H L L L H X H L L->H High-Z External NOP/Dummy Read, Begin Burst
X X X L H X X H L L->H High-Z Next Dummy Read, Continue Burst
L H L L L L L X L L->H D External Write Cycle, Begin Burst
X X X L H X L X L L->H D Next Write Cycle, Continue Burst
L H L L L L H X L L->H High-Z None NOP/Write Abort, Begin Burst
X X X L H X H X L L->H High-Z Next Write Abort, Continue Burst
XX X L X X
X
X
H L->H
-
Current Ignore Clock edge, Stall
X X X H X X X X X X High-Z None Snooze Mode
Note8. X means "don't care". H means logic HIGH. L means logic LOW.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
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