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2001.4.11 Ver. 2.0
M5M5W816TP-70HI, 85HI
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
DESCRIPTION
FEATURES
The M5M5W816TP is a f amily of low v oltage 8-Mbit static
RAMs organized as 524288-words by 16-bit, f abricated by
Mitsubishi's high-perf ormance 0.18µm CMOS technology .
The M5M5W816TP is suitable f or memory applications
where a simple interf acing , battery operating and battery
backup are the important design objectiv es.
The M5M5W816TP is packaged in a 44pin thin small
outline mount dev ice, with the outline of 400mil TSOP
TY PE(II). It giv es the best solution f or a compaction of
mounting area as well as f lexibility of wiring pattern of
printed circuit boards.
The operating temperature range is -40~+85°C
- Single 2.7~3.0V power supply
- Small stand-by current: 0.2µA (3.0V, ty p.)
- No clocks, No ref resh
- Data retention supply v oltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S#, BC1# and BC2#
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE# prev ents data contention in the I/O bus
- Process technology : 0.18µm CMOS
- Package: 44pin 400mil TSOP TYPE(II)
Version,
Operating
temperature
I-version
-40~+85°C
Part name
M5M5W816TP -70HI
M5M5W816TP -85HI
Power
Supply
2.7~3.0V
Access time
max.
Stand-by c urrent
* Ty pical
Ratings (max.)
25°C 40°C 25°C 40°C 70°C 85°C
70ns
85ns
0.5 1.0 2 4 20 40
Activ e
current
Icc1
*(ty p.)
40mA
(10MHz)
5mA
(1MHz)
* Typical parameter indicates the value for the
center of distribution, and not 100% tested.
PIN CONFIGURATION
A4
A3
A2
A1
A0
S#
DQ1
DQ2
DQ3
DQ4
VCC
GND
DQ5
DQ6
DQ7
DQ8
W#
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE#
40 BC2#
39 BC1#
38 DQ16
37 DQ15
36 DQ14
35 DQ13
34 GND
33 VCC
32 DQ12
31 DQ11
30 DQ10
29 DQ9
28 A18
27 A8
26 A9
25 A10
24 A11
23 A17
44Pin 400mil TSOP
Outline: 44P3W
NC: No Connection
Pin Function
A0 ~ A18 Address input
DQ1 ~ DQ16 Data input / output
S#
W#
OE#
Chip select input
Write control input
Output enable input
BC1#
BC2#
Lower By te (DQ1 ~ 8)
Upper By te (DQ9 ~ 16)
Vcc Power supply
GND Ground supply
MITSUBISHI ELECTRIC
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2001.4.11 Ver. 2.0
M5M5W816TP-70HI, 85HI
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W816TP is organized as 524288-words by 16-
bit. These dev ices operate on a single +2.7~3.0V power
supply , and are directly TTL compatible to both input and
output. Its f ully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S# , W# and
OE#. Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S#. The address(A0~A18) must be set up bef ore the
write cy c le and must be stable during the entire cy c le.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S# are in an activ e state(S#=L).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
The operating temperature range is -40 ~ +85°C
When setting BC1# and BC2# at a high lev el or S# at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with other
chips and memory expansion by BC1#, BC2# and S#.
The power supply c urrent is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S# BC1# BC2# W# OE# Mode DQ1~8 DQ9~16 Icc
H X X X X Non selection High-Z High-Z Standby
X H H X X Non selection High-Z High-Z Standby
L L H L X Write Din High-Z Activ e
L L H H L Read Dout High-Z Activ e
L L HHH
High-Z High-Z Activ e
L H L L X Write High-Z Din Activ e
L H L H L Read High-Z Dout Activ e
L H L HH
High-Z High-Z Activ e
L L L L X Write Din Din Activ e
L L L H L Read Dout Dout Activ e
L L LHH
High-Z High-Z Activ e
BLOCK DIAGRAM
A0
A1
MEMORY ARRAY
524288 WORDS
x 16 BITS
A17 -
A18
CLOCK
GENERATOR
S#
DQ
1
DQ
8
DQ
9
DQ
16
BC1#
BC2#
W#
OE#
Vcc
GND
MITSUBISHI ELECTRIC
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2001.4.11 Ver. 2.0
M5M5W816TP-70HI, 85HI
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply v oltage
VI Input v oltage
VO Output v oltage
Pd Power dissipation
Operating
T a temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta= 25°C
T stg Storage temperature
Ratings
-0.3* ~ +4.6
-0.3* ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
700
Units
V
mW
- 40 ~ +85
°C
- 65 ~ +150
°C
* -3.0V in case of AC (Pulse width <= 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=2.7 ~ 3.0V, unless otherwise noted)
Symbol
Parameter
Conditions
VIH High-lev el input v oltage
VIL Low-lev el input v oltage
VOH High-level output voltage IOH= - 0.5mA
VOL Low-lev el output v oltage IOL=2mA
II Input leakage current
VI =0 ~ Vcc
IO Output leakage current
Icc1 Activ e supply c urrent
( AC,MOS lev el )
BC1# and BC2#=VIH or S#=VIH or OE#=VIH, VI/O=0 ~ Vcc
BC1# and BC2# =< 0.2V, S# <= 0.2V
other inputs <= 0.2V or => Vcc-0.2V
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Activ e supply c urrent
Icc2
( AC,TTL lev el )
BC1# and BC2#=V IL , S#=V IL
other pins =V IH or VIL
Output - open (duty 100%)
f = 10MHz
f = 1MHz
Min
2.2
-0.2 *
2.4
-
-
-
-
Limits
Ty p Max Units
Vcc+0.2V
0.6
V
0.4
±1 µA
±1
30 40
5 10
30 40
mA
5 10
Icc3 Stand by s upply current
( AC,MOS lev el )
(1) S# => Vcc - 0.2V,
other inputs = 0 ~ Vcc
(2) BC1# and BC2#=> Vcc - 0.2V
S# <= 0.2V
other inputs = 0 ~ Vcc
~ +25°C
~ +40°C
~ +70°C
~ +85°C
- 0.5 2
- 1.0 4
- - 20 µA
- - 40
Icc4
Stand by s upply current
( AC,TTL lev el )
BC1# and BC2#=VIH or S#=VIH
Other inputs= 0 ~ Vcc
- - 2 mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
* -3.0V in case of AC (Pulse width <= 30ns)
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
CAPACITANCE
Symbol
Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
(Vcc=2.7 ~3.0V, unless otherwise noted)
Limits
Min Ty p Max
10
10
Units
pF
MITSUBISHI ELECTRIC
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2001.4.11 Ver. 2.0
M5M5W816TP-70HI, 85HI
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~3.0V, unless otherwise noted)
(1) TEST CONDITIONS
Supply v oltage
2.7~3.0V
Input pulse
VIH=2.4V, VIL=0.4V
Input rise time and f all time 5ns
Ref erence lev el
V OH=V OL= 1 . 5 V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
DQ
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
1TTL
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
ten(BC1,2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S# high
Output disable time af t er BC1# high
Output disable time af t er BC2# high
Output disable time af t er OE# high
Output enable time af ter S# low
Output enable time af ter BC1#,BC2# low
Output enable time af ter OE# low
Data v alid time after address
Limits
70HI
Min Max
70
70
70
70
70
35
25
25
25
25
10
5
5
10
85HI
Min Max
85
85
85
85
85
45
30
30
30
30
10
5
5
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*5ns in case of using either BC1# or BC2#
(3) WRITE CYCLE
Symbol
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
Limits
70HI
Min Max
70
55
0
65
65
65
65
35
0
0
25
25
5
5
85HI
Min Max
85
60
0
70
70
70
70
45
0
0
30
30
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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2001.4.11 Ver. 2.0
M5M5W816TP-70HI, 85HI
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
(4)TIMING DIAGRAMS
Read cycle
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCR
A 0~18
ta(A)
tv (A)
BC1#,BC2#
(Note3)
ta(BC1) or ta(BC2)
tdis (BC1) or tdis (BC2)
(Note3)
S#
(Note3)
ta(S)
tdis (S)
(Note3)
OE#
W# = "H" lev el
DQ1~16
(Note3)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S)
tdis (OE)
VALID DATA
(Note3)
Write cycle ( W# control mode )
tCW
A 0~18
BC1#,BC2#
S#
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S)
OE#
W#
DQ1~16
tsu (A)
tsu (A-WH)
tw (W)
tdis (W)
tdis(OE)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
(Note3)
(Note3)
MITSUBISHI ELECTRIC
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