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1999.1.15 Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Those are summarized in the part name table below.
DESCRIPTION
The M5M5W816 is a family of low voltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.18µm CMOS technology.
The M5M5W816 is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5W816WG is packaged in a CSP (chip scale package),
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It gives the best solution for a compaction
of mounting area as well as flexibility of wiring pattern of printed
circuit boards.
From the point of operating temperature, the family is divided
into two versions; "Standard" and "I-version".
FEATURES
- Single 1.8~2.7V power supply
- Small stand-by current: 0.1µA (2.7V, typ.)
- No clocks, No refresh
- Data retention supply voltage =1.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1, S2, BC1 and BC2
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prevents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.0mm x 8.5mm CSP
Version,
Operating
temperature
Standard
0 ~ +70°C
I-version
-40 ~ +85°C
Part name
M5M5W816WG -85L
M5M5W816WG -10L
M5M5W816WG -85H
M5M5W816WG -10H
M5M5W816WG -85LI
M5M5W816WG -10LI
M5M5W816WG -85HI
M5M5W816WG -10HI
Power
Supply
1.8 ~ 2.7V
1.8 ~ 2.7V
1.8 ~ 2.7V
1.8 ~ 2.7V
PIN CONFIGURATION
(TOP VIEW)
Access time
max.
85ns
100ns
85ns
100ns
85ns
100ns
85ns
100ns
Stand-by current (Vcc=2.7V)
* Typical
Ratings (max.)
25°C 40°C 25°C 40°C 70°C 85°C
0.1 0.2 --- --- 16 ---
0.1 0.2 1 2 8 ---
0.1 0.2 --- --- 16 30
0.1 0.2 1 2 8 15
Active
current
Icc1
(2.7V, typ.)
40mA
(10MHz)
5mA
(1MHz)
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
1 23 456
A BC1 OE A0 A1 A2 S2
B DQ9 BC2 A3 A4 S1 DQ1
C DQ10 DQ11 A5
A6 DQ2 DQ3
D GND DQ12 A17 A7 DQ4 VCC
E VCC DQ13 GND A16 DQ5 GND
F DQ15 DQ14 A14 A15 DQ6 DQ7
G DQ16 N.C. A12 A13
W DQ8
H A18 A8 A9 A10 A11 N.C.
Outline: 48FHA
NC: No Connection
Pin Function
A0 ~ A18 Address input
DQ1 ~ DQ16 Data input / output
S1 Chip select input 1
S2 Chip select input 2
W Write control input
OE Output enable input
BC1 Lower Byte (DQ1 ~ 8)
BC2 Upper Byte (DQ9 ~ 16)
Vcc Power supply
GND Ground supply
MITSUBISHI ELECTRIC
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1999.1.15 Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W816WG is organized as 524288-words by 16-
bit. These devices operate on a single +1.8~2.7V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no refresh,
and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S1, S2 , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low level
S1 and the high level S2. The address(A0~A18) must be set
up before the write cycle and must be stable during the entire
cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S1 and S2
are in an active state(S1=L,S2=H).
When setting BC1 at the high level and other pins are in an
active stage , upper-byte are in a selectable mode in which
both reading and writing are enabled, and lower-byte are in a
non-selectable mode. And when setting BC2 at a high level
and other pins are in an active stage, lower-byte are in a
selectable mode and upper-byte are in a non-selectable
mode.
BLOCK DIAGRAM
When setting BC1 and BC2 at a high level or S1 at a high level
or S2 at a low level, the chips are in a non-selectable mode in
which both reading and writing are disabled. In this mode, the
output stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S1, S2.
The power supply current is reduced as low as 0.1µA(25°C,
typical), and the memory data can be held at +1V power supply,
enabling battery back-up operation during power failure or
power-down operation in the non-selected mode.
FUNCTION TABLE
S1 S2 BC1 BC2 W OE Mode DQ1~8 DQ9~16 Icc
H L X X X X Non selection High-Z High-Z Standby
L L X X X X Non selection High-Z High-Z Standby
H H X X X X Non selection High-Z High-Z Standby
X X H H X X Non selection High-Z High-Z Standby
L H L H L X Write Din High-Z Active
L H L H H L Read Dout High-Z Active
LH L HH H
High-Z High-Z Active
L H H L L X Write High-Z Din Active
L H H L H L Read High-Z Dout Active
LH H L HH
High-Z High-Z Active
L H L L L X Write Din Din Active
L H L L H L Read Dout Dout Active
LH L LHH
High-Z High-Z Active
A0
A1
MEMORY ARRAY
524288 WORDS
x 16 BITS
A17 -
A18
DQ
1
DQ
8
DQ
9
S1
CLOCK
GENERATOR
S2
DQ
16
BC1
BC2
Vcc
W
GND
OE
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1999.1.15 Ver. 0.1
MITSUBISHI LSIs
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO Output voltage
Pd Power dissipation
Operating
Ta temperature
Tstg Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25C
Standard (-L, -H)
I-version (-LI, -HI)
Ratings
-0.5* ~ +4.6
-0.2* ~ Vcc + 0.2 (max. 4.6V)
0 ~ Vcc
700
0 ~ +70
- 40 ~ +85
- 65 ~ +150
* -3.0V in case of AC (Pulse width <= 30ns)
Units
V
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS
( Vcc=1.8 ~ 2.7V, unless otherwise noted)
Symbol
Parameter
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage
VOL Low-level output voltage
II Input leakage current
IO Output leakage current
Icc1 Active supply current
( AC,MOS level )
Active supply current
Icc2
( AC,TTL level )
Icc3 Stand by supply current
( AC,MOS level )
Stand by supply current
Icc4
( AC,TTL level )
Conditions
IOH= -0.1mA
IOL=0.1mA
VI =0 ~ Vcc
BC1 and BC2=VIHor S1=VIHor S2=VIL or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2<= 0.2V, S1<= 0.2V, S2 Vcc-0.2V
other inputs <=0.2V or => Vcc-0.2V
Output - open (duty 100%)
f= 10MHz
f= 1MHz
BC1 and BC2=VIL , S=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
f= 10MHz
f= 1MHz
(1) S1 => Vcc - 0.2V,
other inputs = 0 ~ Vcc
(2) S2=> 0.2V,
other inputs = 0 ~ Vcc
(3) BC1 and BC2 =>Vcc - 0.2V
S1 <=0.2V, S2 =>Vcc - 0.2V
other inputs = 0 ~ Vcc
-H, -HI
-HI
-L, -LI
-LI
~ +25°C
~ +40°C
~ +70°C
~ +85°C
~ +70°C
~ +85°C
BC1 and BC2=VIH or S1=VIH or S2=VIL
Other inputs= 0 ~ Vcc
Limits
Min Typ
Max Units
0.7 x Vcc
Vcc+0.2V
-0.2 *
1.6
0.4
V
0.2
±1 µA
±1
- 40 50
- 5 10
-
40 50
mA
- 5 10
- 0.1 1
- 0.2 2
--8
- - 15 µA
- - 16
- - 30
- - 0.5 mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
* -1.0V in case of AC (Pulse width =< 30ns)
Note 2: Typical parameter indicates the value for the center of distribution at 2.7V, and not 100% tested.
CAPACITANCE
Symbol Parameter
CI Input capacitance
CO Output capacitance
Conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
(Vcc=1.8 ~ 2.7V, unless otherwise noted)
Limits
Min Typ Max
10
10
Units
pF
MITSUBISHI ELECTRIC
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