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2001.June Rev.0.0
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Notice: This is not final specification.
Some parametric limits are subject to change.
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
DESCRIPTION
The M5M5Y5636TG is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5Y5636TG operates on a single 1.8V
power supply and are 1.8V CMOS compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 1.8V +150/-100mV power supply VDD
• Separate VDDQ for 1.8V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 User programmable chip enable inputs for easy depth
expansion
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control triggered
by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV),
Byte Write Enables (BWa#, BWb#, BWc#, BWd#), Echo Clock
outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write
operations are controlled by the eight Byte Write Enables (BWa#
- BWd#) and Read/Write(W#) inputs. All writes are conducted
with on-chip synchronous self-timed write circuitry.
The Echo Clocks are delayed copies of the RAM clock, CLK.
Echo Clocks are designed to track changes in output driver
delays due to variance in die temperature and supply voltage.
The ZQ pin supplied with selectable impedance drivers, allows
selection between nominal drive strength (ZQ LOW) for multi-
drop bus application and low drive strength (ZQ floating or HIGH)
point-to-point applications.
The sense of two User-Programmable Chip Enable inputs (E2,
E3), whether they function as active LOW or active HIGH inputs,
is determined by the state of the programming inputs, EP2 and
EP3.
The Linear Burst order (LBO#) is DC operated pin. LBO# pin
will allow the choice of either an interleaved burst, or a linear
burst.
All read, write and deselect cycles are initiated by the ADV
Low input. Subsequent burst address can be internally generated
as controlled by the ADV HIGH input.
PACKAGE
M5M5Y5636TG
Bump
209(11X19) bump BGA
Body Size
14mm X 22mm
Bump Pitch
1mm
PART NAME TABLE
Part Name
M5M5Y5636TG -25
M5M5Y5636TG -22
M5M5Y5636TG -20
Frequency
250MHz
225MHz
200MHz
Access
2.6ns
2.8ns
3.2ns
Cycle
4.0ns
4.4ns
5.0ns
Active Current
(max.)
400mA
380mA
360mA
Standby Current
(max.)
20mA
20mA
20mA
1
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BUMP LAYOUT(TOP VIEW)
209 bump BGA
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
1 2 3 4 5 6 7 8 9 10 11
A NC NC A6 E2 A7 ADV A8 E3 A9 DQb DQb
B NC NC BWc# NC A18 W# A17 BWb# NC DQb DQb
C NC NC NC BWd# NC E1# NC NC BWa# DQb DQb
D NC NC VSS NC NC MCL NC NC VSS DQb DQb
E NC DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC DQPb
F DQc DQc VSS VSS VSS ZQ VSS VSS VSS NC NC
G DQc DQc VDDQ VDDQ VDD EP2 VDD VDDQ VDDQ NC NC
H DQc DQc VSS VSS VSS EP3 VSS VSS VSS NC NC
J
DQc DQc VDDQ VDDQ VDD MCH VDD VDDQ VDDQ NC
NC
K CQ2 CQ2# CLK NC VSS MCL VSS NC NC CQ1# CQ1
L NC NC VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQa DQa
M NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
N NC NC VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQa DQa
P NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
R DQPd NC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa NC
T DQd DQd VSS NC NC LBO# NC NC VSS NC NC
U DQd DQd NC A3 NC A15 NC A11 NC NC NC
V DQd DQd A5
A4 A16 A1 A13 A12 A10 NC NC
W DQd DQd TMS TDI A2 A0 A14 TDO TCK NC NC
Note1. MCH means “Must Connect High”. MCH should be connected to HIGH.
Note2. MCL means “Must Connect Low”. MCL should be connected to LOW.
2
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BLOCK DIAGRAM
A0
A1
A2~18
LBO#
CLK
19
MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
VDD
VDDQ
ADDRESS
REGISTER
19 17
A1
D1
A0
D0
LINEAR/
INTERLEAVED
BURST
COUNTER
A1'
Q1
A0'
Q0
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
19
19
ADV
BWa#
BWb#
BWc#
BWd#
W#
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
BYTE a
|
BYTE d
WRITE
DRIVERS
256Kx36
MEMORY
ARRAY
INPUT
36 REGISTER1
INPUT
REGISTER0
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
E1#
E2
E3
EP2
EP3
ZQ
CHIP ENABLE
CONTROL
LOGIC
READ
LOGIC
VSS
Note3. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note4. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
CQ1
CQ1#
CQ2
CQ2#
3
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION
Pin
A0~A18
BWa#, BWb#,
BWc#, BWd#
CLK
E1#
E2, E3
EP2, EP3
ADV
CQ1, CQ1#,
CQ2, CQ2#
ZQ
W#
DQa,DQPa,DQb,DQPb,
DQc,DQPc,DQd,DQPd
LBO#
VDD
VSS
VDDQ
TDI
TDO
TCK
TMS
MCH
MCL
NC
Name
Synchronous
Address
Inputs
Synchronous
Byte Write
Enables
Clock Input
Synchronous
Chip Enable
Synchronous
Chip Enable
Chip Enable
Program Pin
Synchronous
Address
Advance/Load
Echo Clock
Outputs
Output
Impedance
Control
Synchronous
Read/Write
Synchronous
Data I/O
Burst Mode
Control
VDD
VSS
VDDQ
Test Data Input
Test Data Output
Test Clock
Test Mode Select
Must Connect High
Must Connect Low
No Connect
Function
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWa are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
This signal registers the address, data, chip enables, byte write enables and burst control inputs on
its rising edge.
All synchronous inputs must meet setup and hold times around the clock's rising edge.
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
These pins are user-programmable chip enable inputs. The sense of the inputs, whether they
function as active LOW or HIGH inputs, is determined by the state of the programming inputs, EP2
and EP3.
These pins determine the sense of the user-programmable chip enable inputs, whether they
function as active LOW or active HIGH inputs.
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
The Echo Clocks are delayed copies of the main RAM clock, CLK.
This pin allows selection between RAM nominal drive strength (ZQ low) for multi-drop bus
applications and low drive strength (ZQ floating or high) point-to-point application.
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
Core Power Supply
Ground
I/O buffer Power supply
These pins are used for Boundary Scan Test.
These pins should be connected to HIGH
These pins should be connected to LOW
These pins are not internally connected and may be connected to ground.
4
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Read Operation
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3)
are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low. The address presented to the address inputs
is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access
is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data
is allowed to propagate through the output register and onto the output pins.
CLK
E1#
ADV
W#
BWx#
ADD
DQ
CQ
A
Read A
Deselect
B
Q(A)
Read B
CDE
Q(B)
Q(C)
Read C
Read D
Read E
5
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