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MITSUBISHI<Dig.Ana.INTERFACE>
M62354P,FP,GP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62354 is an integrated circuit semiconductor of CMOS
structure with 6 channels of built-in D-A converters with output
buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer
format mum wiring.
It is able to cascading serial use with Do terminal.
The output buffer operational amplifier operates in the whole
voltage range from power supply to ground for both
input/output.
FEATURES
•12bit serial data input(3-wire serial data transfer method)
•Highly stable output buffer operational amplifier allow operation
in the all voltage range from power supply to ground.
PIN CONFIGURATION (TOP VIEW)
DO 1
LD 2
CLK 3
DI 4
Ao1 5
Ao2 6
GND 7
14 Vcc
13 VDD
12 Ao6
11 Ao5
10 Ao4
9 Ao3
8 Vss
Outline 14P4(P)
14P2N-A(FP)
APPLICATION
Adjustment/control of industrial or home-use electronic
equipment,such as VTR camera,VTR set,TV,and CRT
display.
DO 1
LD 2
CLK 3
DI 4
Ao1 5
Ao2 6
NC 7
GND 8
16 Vcc
15 VDD
14 Ao6
13 Ao5
12 Ao4
11 Ao3
10 NC
9 Vss
BLOCK DIAGRAM
Outline 16P2E-A(GP)
NC:NO CONNECTION
Vcc VDD Ao6
Ao5 Ao4 Ao3
Vss
14 13 12 11 10
9
8
BUFFER
- - - - OP AMP
D-A
Ch6
L
D-A
5
L
D-A
4
L
8-BIT
R-2R D-A
3
8-BIT
LATCH
(6)
ADDRESS
DECODER
D11 10 9 D8
D7 6 5 4 3 2 1 D0
12-BIT SHIFT REGISTER
12
34
Do LD CLK DI
(6)
L
Ch1
D-A
-
5
Ao1
8-BIT
LATCH
2
8-BIT
R-2R D-A
-
BUFFER
OP AMP
67
Ao2 GND
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EXPLANATION OF TERMINALS
Pin No.
4 ( 4 )*
1 (1)
3 (3)
2 (2 )
5 (5 )
6 (6 )
9 ( 11 )
10 ( 12 )
11 ( 13 )
12 ( 14 )
14 ( 16 )
7 (8)
13 ( 15 )
8 (9 )
Symbol
DI
DO
CLK
LD
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
Vcc
GND
VDD
Vss
*( ):16P2E
MITSUBISHI<Dig.Ana.INTERFACE>
M62354P,FP,GP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Function
Serial data input terminal
Serial data output terminal
Serial clock input terminal
LD terminal input high level than latch circuit data load
8-bit D-A converter output terminal
Power supply terminal
Digital and analog common GND
D-A converter upper reference voltage input terminal
D-A converter lower reference voltage input terminal
BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS
DI 4
CLK 3
Vcc GND
14 7
12-BIT SHIFT REGISTER
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
86
ADDRESS DECODER
1234 5 6
1 D0
2 LD
D0 ............ D7
1 8-BIT
LATCH
..............................................6
D0 ............
8-BIT
LATCH
D7
8-BIT
R-2R D-A
..............................................
8-BIT
R-2R D-A
-
...................................................................................................
-
13
VDD
(VrefU)
5
Ao1
12
Ao12
8
VSS
(VrefL)
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MITSUBISHI<Dig.Ana.INTERFACE>
M62354P,FP,GP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DIGITAL DATA FORMAT
LAST
LSB
FIRST
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
DAC DATA
DAC SELECT DATA
D0 D1 D2
000
100
010
110
0 11
1 11
D8 D9 D10
00 0
00 0
00 1
00 1
01 0
01 0
01 1
01 1
100
100
101
101
110
110
111
111
TIMING CHART (MODEL)
D3 D4 D5 D6
00
00
00
00
00
00
00
00
11
11
11
11
D11 DAC selection
0 Don’t care
1 Ao1 selection
0 Ao2
1 Ao3
0 Ao4
1 Ao5
0 Ao6
1 Ao7
0 Ao8
1 Ao9
0 Ao10
1 Ao11
0 Ao12
1 Don’t care
0 Don’t care
1 Don’t care
D7 D-A output
0 (VrefU-VrefL)/256X1+VrefL
0 (VrefU-VrefL)/256X2+VrefL
0 (VrefU-VrefL)/256X3+VrefL
0 (VrefU-VrefL)/256X4+VrefL
1 (VrefU-VrefL)/256X255+VrefL
1 VrefU
*VrefU=VDD
VrefL=Vss
MSB
DI D11 D10 D9 D8
CLK
LSB
D2 D1 D0
LD
D-A
OUTPUT
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MITSUBISHI<Dig.Ana.INTERFACE>
M62354P,FP,GP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VDD
VIN
Vo
Pd
Topr
Tstg
Parameter
Supply voltage
D-A converter upper reference voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
Ratings
-0.3~7.0
-0.3~7.0
-0.3~Vcc+0.3
-0.3~Vcc+0.3
440(P)/250(FP)/150(GP)
-20~+85
-55~+125
ELECTRICAL CHARACTERISTICS
Digital part(Vcc,VrefU=+5V±10%,VccVrefU,GND,VrefL=0V,Ta=-20°C~+85°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min. Typ.
Vcc Supply voltage
4.5 5.0
Max.
5.5
Icc Circuit current
CLK=1MHz operation
IOA=0µA
1.6 3.2
IILK Input leak current
VIL Input low voltage
VIH Input high voltage
VOL Output low voltage
VOH Output high voltage
VIN=0~Vcc
IOL=2.5mA
IOH=-400µA
-10
0.8Vcc
10
0.2Vcc
Vcc-0.4
0.4
Unit
V
V
V
V
mV
°C
°C
Unit
V
mA
µA
V
V
V
V
Analog part(Vcc,VrefU=+5V±10%,VccVrefU,Ta=-20°C~+85°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
IDD Current dissipation
VrefU=5V,VrefL=0V
Data condition;at maximum current
VDD
Vss
VAO
IAO
SDL
SL
SZERO
SFULL
CO
RO
D-A converter upper reference
voltage range
D-A converter lower reference
voltage range
The output dose not necessarily be the value
within the reference voltage setting range.
The output value is determined by the buffer
amplifier output voltage range(VAO)
Buffer amplifier
output voltage range
Buffer amplifier
output drive range
IOA=±100µA
IOA=±500µA
Upper side saturation voltage=0.3V
Lower side saturation voltage=0.2V
Differential nonlinearity error
Nonlinearity error
Zero code error
Full scale error
VrefU=4.79V
VrefL=0.95V
Vcc=5.5V(15mV/LSB)
Without load(IOA=±0)
Output capacitive load
Buffer amplifier output impedance
3.5
GND
0.1
0.2
-1
-1.0
-1.5
-2
-2
Limits
Typ.
0.7
Max.
1.3
Vcc
Vcc-3.5
Vcc-0.1
Vcc-0.2
1
1.0
1.5
2
2
0.1
5
Unit
mA
V
V
V
mA
LSB
LSB
LSB
LSB
µF
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MITSUBISHI<Dig.Ana.INTERFACE>
M62354P,FP,GP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
AC CHARACTERISTICS(Vcc,VrefU=+5V±10%,VccVrefU,GND,VrefL=0V,Ta=-20~+85°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min Typ Max
tCLK Clock "L"pulse width
200
tCKH Clock "H"pulse width
200
tCR Clock rise time
200
tCF Clock fall time
200
tDCH
Data setup time
30
tCHD
Data hold time
60
tCHL LD setup time
200
tLDC LD hold time
100
tLDH LD "H" pulse width
100
tDO Data output delay time
CL100pF
70 350
tLDD D-A output setting time
CL100pF VAQ:0.5 4.5V
The time until the output becomes the
final value of 1/2 LSB
300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
TIMING CHART
CLK
tCR tCKH tCF
tCKL
DI
LD
D-A
OUTPUT
DO
OUTPUT
tDCH tCHD
tCHL
tDO
tLDH
tLDC
tLDD
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