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Triple 8-Bit Analog-to-Digital-Converter
SDA 9205-2
Preliminary Data
Features
q Three equivalent CMOS A/D converters on chip
q 30-MHz sample rate
q 8-bit resolution
q No external sample & hold required
q On-chip input buffer for each analog channel
q Internal clamping circuits for each of the ADCs
q Different digital output multiplex formats:
– 3 independent unmultiplexed 8-bit outputs
– Multiplexed formats compatible to inputs of all
Siemens Featureboxes and Siemens TV-SAM
– CCIR 656 output format
q Overflow and underflow outputs
CMOS IC
P-LCC-68-1
Type
SDA 9205-2
Ordering Code
Q67100-H5069
Package
P-LCC-68-1 (SMD)
General Description
The SDA 9205-2 is a single monolithic IC containing three separate 8-bit analog to digital converters
for video (YUV) applications. It utilizes an advanced VLSI 1.2 µm CMOS process providing 30-MHz
sampling rates at 8 bits. Different digital output multiplex formats are selectable on chip via several
control inputs, compatible to inputs of all Siemens Featureboxes, Siemens TV-SAM, and CCIR 656
output format.
The ADCs have no missing codes over the full operating temperature range of 0 to + 70 °C.
Operation is from + 5 V DC-power supply.
Semiconductor Group
1
01.94

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Pin Configuration
(top view)
SDA 9205-2
Semiconductor Group
2

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SDA 9205-2
Pin Definitions and Functions
Pin No.
63 to 2
3
4
5
6
7
8/9/11/17
10
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27/29
28
30
31
32
33
34 to 41
42
43
Symbol
C7 to C0
VQGNDC
UFLC
OFLC
OENC
DTC
CONT3-
CONT0
VREFHC
VCCC
VAGNDC
VREFLC
AINC
VREFHB
VCCB
VAGNDB
VREFLB
AINB
VREFHA
VCCA
VAGNDA
AINA
VREFLA
TEST
DTA
CLAMP
UFLA
OFLA
VQGNDA
A7 to A0
OENA
VDDQA
Function
Digital outputs of ADC C (port C) C0 least significant bit
Output stages supply ground of port C
Underflow data output of ADC C
Overflow data output of ADC C
Output enable of port C
Binary/two’s complement output port C
Control inputs for different digital output multiplex formats –
refer to logic table
Reference voltage high of ADC C (+ 2.5 V)
Analog positive supply voltage of ADC C (+5 V)
Analog ground of ADC C
Reference voltage low of ADC C (+ 5 V)
Analog voltage input of ADC C
Reference voltage high of ADC B (+ 2.5 V)
Analog positive supply voltage of ADC B (+ 5 V)
Analog ground of ADC B
Reference voltage low of ADC B (+ 0.5 V)
Analog voltage input of ADC B
Reference voltage high of ADC A (+ 2.5 V)
Analog positive supply voltage of ADC A (+ 5 V)
Analog ground of ADC A
Analog voltage input of ADC A
Reference voltage low of ADC A (+ 0.5 V)
Factory use only, connect to 0 V
Binary/two’s complement output of port A
Clamp input for all three channels
Underflow data output of ADC A
Overflow data output of ADC A
Output stages supply ground of port A
Digital outputs of ADC A (port A) A0 least significant bit
Output enable of port A
Output stages supply voltage of port A
Semiconductor Group
3

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SDA 9205-2
Pin Definitions and Functions (cont’d)
Pin No.
44
45
46
47
48 to 55
56
57
58
59
60
61
62
Symbol
OENB
UFLB
OFLB
VQGNDB
B7 to B0
VDDQB
CLK
VDGND
FSY
DTB
VDD
VDDQC
Function
Output enable of port B
Underflow data output of ADC B
Overflow data output of ADC B
Output stages supply ground of port B
Digital outputs of ADC B (port B) B0 least significant bit
Output stages supply voltage of port B
Clock input
Digital ground
Format sync input
Binary/two’s complement output of port B
Digital positive supply voltage (+ 5 V)
Output stages supply voltage of port C
Semiconductor Group
4

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SDA 9205-2
Circuit Description
Analog to Digital Converter
The SDA 9205-2 implements 3 independent 8-bit analog-to-digital converters.
They are two step converters with a coarse comparator block and two fine comparator blocks each
using pipeline architecture for high speed sampling performance. During the first clock cycle, the
coarse comparator samples and determines 4 MSBs and one of the fine comparator blocks
samples the input voltage. During the second clock cycle this fine comparator block makes its
decision for the 4 LSBs. So the coarse comparator block makes its decisions at each clock cycle,
the fine comparator blocks make the comparison alternating every two clock cycles.
The converter uses the redundancy principle to correct fine conversion. The sample and hold
function has been distributed in each comparator due to the two step conversion principle.
Clamping
An internal clamping circuit is provided in each of three analog channels. The analog pins AINA,
AINB, AINC are switched simultaneously to on chip generated clamping levels by an active high
pulse on pin 30 (CLAMP).
Clamping Levels
Analog Channel
AINA
AINB, AINC
Dual Code
00010000
10000000
Components
(Y)
(U, V)
Semiconductor Group
5