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80186 80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y Integrated Feature Set
Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller
Y Available in 10 MHz and 8 MHz
Versions
Y High-Performance Processor
4 Mbyte Sec Bus Bandwidth
Interface 8 MHz (80186)
5 Mbyte Sec Bus Bandwidth
Interface 10 MHz (80186)
Y Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O
Y Completely Object Code Compatible
with All Existing 8086 8088 Software
10 New Instruction Types
Y Numerics Coprocessing Capability
Through 8087 Interface
Y Available in 68 Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)
Y Available in EXPRESS
Standard Temperature with Burn-In
Extended Temperature Range
(b40 C to a85 C)
Figure 1 Block Diagram
272430 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
Order Number 272430-002
COPYRIGHT INTEL CORPORATION 1995
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80186 80188 High-Integration 16-Bit Microprocessors
CONTENTS
FUNCTIONAL DESCRIPTION
Introduction
CLOCK GENERATOR
Oscillator
Clock Generator
READY Synchronization
RESET Logic
LOCAL BUS CONTROLLER
Memory Peripheral Control
Local Bus Arbitration
Local Bus Controller and Reset
PERIPHERAL ARCHITECTURE
Chip-Select Ready Generation Logic
DMA Channels
Timers
Interrupt Controller
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CONTENTS
ABSOLUTE MAXIMUM RATINGS
D C CHARACTERISTICS
A C CHARACTERISTICS
EXPLANATION OF THE AC
SYMBOLS
WAVEFORMS
EXPRESS
EXECUTION TIMINGS
INSTRUCTION SET SUMMARY
FOOTNOTES
REVISION HISTORY
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Contacts Facing Up
80186 80188
Contacts Facing Down
Figure 2 Ceramic Leadless Chip Carrier (JEDEC Type A)
Pins Facing Up
Pins Facing Down
272430 – 2
Figure 3 Ceramic Pin Grid Array
NOTE
Pin names in parentheses apply to the 80188
272430 – 3
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80186 80188
Leads Facing Up
Leads Facing Down
Figure 4 Plastic Leaded Chip Carrier
NOTE
Pin names in parentheses apply to the 80188
272430 – 4
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80186 80188
Table 1 Pin Descriptions
Symbol
Pin
No Type
Name and Function
VCC 9 I SYSTEM POWER a5 volt power supply
43
VSS 26 I System Ground
60
RESET
57 O Reset Output indicates that the CPU is being reset and can be used as a system
reset It is active HIGH synchronized with the processor clock and lasts an
integer number of clock periods corresponding to the length of the RES signal
X1 59 I Crystal Inputs X1 and X2 provide external connections for a fundamental mode
X2 58 O parallel resonant crystal for the internal oscillator Instead of using a crystal an
external clock may be applied to X1 while minimizing stray capacitance on X2
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT)
CLKOUT
56 O Clock Output provides the system with a 50% duty cycle waveform All device
pin timings are specified relative to CLKOUT
RES
24 I An active RES causes the processor to immediately terminate its present
activity clear the internal logic and enter a dormant state This signal may be
asynchronous to the processor clock The processor begins fetching
instructions approximately 6 clock cycles after RES is returned HIGH For
proper initialization VCC must be within specifications and the clock signal must
be stable for more than 4 clocks with RES held LOW RES is internally
synchronized This input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network
TEST
47 I O TEST is examined by the WAIT instruction If the TEST input is HIGH when
‘‘WAIT’’ execution begins instruction execution will suspend TEST will be
resampled until it goes LOW at which time execution will resume If interrupts
are enabled while the processor is waiting for TEST interrupts will be serviced
During power-up active RES is required to configure TEST as an input This pin
is synchronized internally
TMR IN 0
TMR IN 1
20 I Timer Inputs are used either as clock or control signals depending upon the
21 I programmed timer mode These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized
TMR OUT 0
TMR OUT 1
22 O Timer outputs are used to provide single pulse or continous waveform
23 O generation depending upon the timer mode selected
DRQ0
DRQ1
18 I DMA Request is asserted HIGH by an external device when it is ready for DMA
19 I Channel 0 or 1 to perform a transfer These signals are level-triggered and
internally synchronized
NMI 46 I The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition
from LOW to HIGH is latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be asserted for at least one
clock The Non-Maskable Interrupt cannot be avoided by programming
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
45
44
42
41
I Maskable Interrupt Requests can be requested by activating one of these pins
I When configured as inputs these pins are active HIGH Interrupt Requests are
I O synchronized internally INT2 and INT3 may be configured to provide active-
I O LOW interrupt-acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To ensure recognition all
interrupt requests must remain active until the interrupt is acknowledged When
Slave Mode is selected the function of these pins changes (see Interrupt
Controller section of this data sheet)
NOTE
Pin names in parentheses apply to the 80188
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