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SPECIAL ENVIRONMENT 80960CA-25 -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
 Two Instructions Clock Sustained Execution
 Four 59 Mbytes s DMA Channels with Data Chaining
 Demultiplexed 32-bit Burst Bus with Pipelining
Y 32-bit Parallel Architecture
Two Instructions clock Execution
Load Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulates 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model
Y Fast Procedure Call Return Model
Full Procedure Call in 4 Clocks
Y On-Chip Register Cache
Caches Registers on Call Ret
Minimum of 6 Frames Provided
Up to 15 Programmable Frames
Y On-Chip instruction Cache
1 Kbyte Two-Way Set Associative
128-bit Path to instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
Y High Bandwidth On-Chip Data RAM
1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access
Y Four On-Chip DMA Channels
59 Mbytes s Fly-by Transfers
32 Mbytes s Two-Cycle Transfers
Data Chaining
Data Packing Unpacking
Programmable Priority Method
Y 32-Bit Demultiplexed Burst Bus
128-bit internal Data Paths to and
from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8- 16- or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
Y Selectable Big or Little Endian Byte
Ordering
Y High-Speed Interrupt Controller
Up to 248 External interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four internal DMA Interrupts
Separate Non-maskable interrupt Pin
Context Switch in 750 ns Typical
Y Product Grades Available
SE3 b40 C to a110 C
December 1994
Order Number 271327-001

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SPECIAL ENVIRONMENT 80960CA-25 -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
CONTENTS
1 0 PURPOSE
2 0 80960CA OVERVIEW
2 1 The C-Series Core
2 2 Pipelined Burst Bus
2 3 Flexible DMA Controller
2 4 Priority Interrupt Controller
2 5 Instruction Set Summary
3 0 PACKAGE INFORMATION
3 1 Package Introduction
3 2 Pin Descriptions
3 3 80960CA Mechanical Data
3 3 1 80960CA PGA Pinout
3 4 Package Thermal Specifications
3 5 Stepping Register Information
3 6 Suggested Sources for 80960CA Accessories
4 0 ELECTRICAL SPECIFICATIONS
4 1 Absolute Maximum Ratings
4 2 Operating Conditions
4 3 Recommended Connections
4 4 DC Specifications
4 5 AC Specifications
4 5 1 AC Test Conditions
4 5 2 AC Timing Waveforms
4 5 3 Derating Curves
5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE
6 0 BUS WAVEFORMS
7 0 REVISION HISTORY
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CONTENTS
LIST OF FIGURES
Figure 1 80960CA Block Diagram
Figure 2 80960CA PGA Pinout View from Top (Pins Facing Down)
Figure 3 80960CA PGA Pinout View from Bottom (Pins Facing Up)
Figure 4 Measuring 80960CA PGA Case Temperature
Figure 5 Register g0
Figure 6 AC Test Load
Figure 7 Input and Output Clocks Waveform
Figure 8 CLKIN Waveform
Figure 9 Output Delay and Float Waveform
Figure 10 Input Setup and Hold Waveform
Figure 11 NMI XINT7 0 Input Setup and Hold Waveform
Figure 12 Hold Acknowledge Timings
Figure 13 Bus Backoff (BOFF) Timings
Figure 14 Relative Timings Waveforms
Figure 15 Output Delay or Hold vs Load Capacitance
Figure 16 Rise and Fall Time Derating at Highest Operating Temperature
and Minimum VCC
Figure 17 ICC vs Frequency and Temperature
Figure 18 Cold Reset Waveform
Figure 19 Warm Reset Waveform
Figure 20 Entering the ONCE State
Figure 21 Clock Synchronization in the 2-x Clock Mode
Figure 22 Clock Synchronization in the 1-x Clock Mode
Figure 23 Non-Burst Non-Pipelined Requests without Wait States
Figure 24 Non-Burst Non-Pipelined Read Request with Wait States
Figure 25 Non-Burst Non-Pipelined Write Request with Wait States
Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus
Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus
Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus
Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus
Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus
Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus
Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus
Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus
Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus
Figure 35 Burst Pipelined Read Request with Wait States 32-Bit Bus
Figure 36 Burst Pipelined Read Request with Wait States 16-Bit Bus
Figure 37 Burst Pipelined Read Request with Wait States 8-Bit Bus
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