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PRELIMINARY
80960JA/JF
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
Processors
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
s Two-Way Set Associative Instruction Cache s High-Speed Interrupt Controller
— 80960JA - 2 Kbyte
— 80960JF - 4 Kbyte
— Programmable Cache Locking
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JA - 1 Kbyte
— 80960JF - 2 Kbyte
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
— Write Through Operation
s Halt Mode for Low Power
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
— 0-7 Frames Reserved for High-Priority s Packages
Interrupts
— 132-Lead Pin Grid Array (PGA)
s On-Chip Data RAM
— 132-Lead Plastic Quad Flat Pack (PQFP)
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
iA80960Jx
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PIN 1
132
33
A
i960®
iNG80960Jx
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66
Figure 1. 80960JA/JF Microprocessors
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272504-004

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80960JA/JF
80960JA/JF
EMBEDDED 32-BIT MICROPROCESSOR
1.0 PURPOSE ..................................................................................................................................................1
2.0 80960JA/JF OVERVIEW ............................................................................................................................1
2.1 80960 Processor Core ........................................................................................................................2
2.2 Burst Bus ............................................................................................................................................2
2.3 Timer Unit ...........................................................................................................................................3
2.4 Priority Interrupt Controller .................................................................................................................3
2.5 Instruction Set Summary ....................................................................................................................3
2.6 Faults and Debugging .........................................................................................................................3
2.7 Low Power Operation .........................................................................................................................4
2.8 Test Features ......................................................................................................................................4
2.9 Memory-Mapped Control Registers ....................................................................................................4
2.10 Data Types and Memory Addressing Modes ....................................................................................4
3.0 PACKAGE INFORMATION ........................................................................................................................6
3.1 Pin Descriptions ..................................................................................................................................6
3.1.1 Functional Pin Definitions ........................................................................................................6
3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13
3.1.3 80960Jx PQFP Pinout ...........................................................................................................17
3.2 Package Thermal Specifications ......................................................................................................20
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................22
4.1 Absolute Maximum Ratings ..............................................................................................................22
4.2 Operating Conditions ........................................................................................................................22
4.3 Connection Recommendations .........................................................................................................22
4.4 DC Specifications .............................................................................................................................23
4.5 AC Specifications ..............................................................................................................................25
4.5.1 AC Test Conditions and Derating Curves ...............................................................................32
4.5.2 AC Timing Waveforms ............................................................................................................33
5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................41
6.0 DEVICE IDENTIFICATION .......................................................................................................................55
7.0 REVISION HISTORY ...............................................................................................................................55
PRELIMINARY
ii

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80960JA/JF
A
FIGURES
Figure 1.
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Figure 28.
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Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
80960JA/JF Microprocessors ....................................................................................................0
80960JA/JF Block Diagram ........................................................................................................2
132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13
132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14
132-Lead PQFP - Top View ..................................................................................................... 17
AC Test Load ............................................................................................................................ 32
Output Delay or Hold vs. Load Capacitance ............................................................................ 32
Rise and Fall Time Derating ..................................................................................................... 33
CLKIN Waveform ..................................................................................................................... 33
Output Delay Waveform for TOV1 ............................................................................................. 34
Output Float Waveform for TOF ................................................................................................ 34
Input Setup and Hold Waveform for TIS1 and TIH1 ................................................................... 35
Input Setup and Hold Waveform for TIS2 and TIH2 ................................................................... 35
Input Setup and Hold Waveform for TIS3 and TIH3 ................................................................... 36
Input Setup and Hold Waveform for TIS4 and TIH4 ................................................................... 36
Relative Timings Waveform for TLXL and TLXA ........................................................................ 37
DT/R and DEN Timings Waveform .......................................................................................... 37
TCK Waveform ......................................................................................................................... 38
Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 .......................................................... 38
Output Delay and Output Float Waveform for TBSOV1 and TBSOF1 .......................................... 39
Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .......................................... 39
Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ........................................................... 40
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 41
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 42
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 43
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 44
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ................................................................................... 45
Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
46
HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 47
Cold Reset Waveform .............................................................................................................. 48
Warm Reset Waveform ............................................................................................................ 49
Entering the ONCE State ......................................................................................................... 50
Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 53
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 54
iii PRELIMINARY