80960KB.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 80960KB 데이타시트 다운로드

No Preview Available !

80960KB
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
s High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached Instruc-
tions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip
— Register Scoreboarding
s 4 Gigabyte, Linear Address Space
s Pin Compatible with 80960KA
s Built-in Interrupt Controller
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
s Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
s On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point Standard
— Four 80-Bit Registers
— 13.6 Million Whetstones/s (Single
Precision) at 25 MHz
The 80960KB is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache, an integrated floating-point unit and a built-in interrupt
controller. The 80960KB has a large register set, multiple parallel execution units and a high-bandwidth burst
bus. Using advanced RISC technology, this high performance processor is capable of execution rates in excess
of 9.4 million instructions per second*. The 80960KB is well-suited for a wide range of applications including non-
impact printers, I/O control and specialty instrumentation.
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
BURST
BUS
Figure 1. The 80960KB Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
May 1993
© INTEL CORPORATION, 1993
Order Number: 270565-006

No Preview Available !

80960KB
1.0 THE i960® PROCESSOR
The 80960KB is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
were especially designed to serve the needs of
embedded applications. The embedded market
includes applications as diverse as industrial
automation, avionics, image processing, graphics and
networking. These types of applications require high
integration, low power consumption, quick interrupt
response times and high performance. Since time to
market is critical, embedded microprocessors need to
be easy to use in both hardware and software
designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
Software written for the 80960KB will run without
modification on any other member of the 80960
Family. It is also pin-compatible with the 80960KA and
the 80960MC which is a military-grade version that
supports multitasking, memory management, multi-
processing and fault tolerance.
0000 0000H
ADDRESS SPACE
FETCH
INSTRUCTION CACHE
INSTRUCTION
STREAM
FFFF FFFFH
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
LOAD
STORE
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
SIXTEEN 32-BIT GLOBAL REGISTERS
g0
g15
REGISTER CACHE
SIXTEEN 32-BIT LOCAL REGISTERS
r0
r15
FOUR 80-BIT FLOATING POINT REGISTERS
CONTROL REGISTERS
Figure 2. 80960KB Programming Environment
1

No Preview Available !

80960KB
1.1. Key Performance Features
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KB’s exceptional
performance:
1. Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the
80960KB provides thirty-two 32-bit registers and four
80-bit floating point registers. (See Figure 2.)
2. Fast Instruction Execution. Simple functions
make up the bulk of instructions in most programs so
that execution speed can be improved by ensuring
that these core instructions are executed as quickly
as possible. The most frequently executed instruc-
tions such as register-register moves, add/subtract,
logical operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of times that
the processor must access memory to perform an
operation. As with other processors based on RISC
technology, the 80960KB has a Load/Store archi-
tecture. As such, only the LOAD and STORE instruc-
tions reference memory; all other instructions operate
on registers. This type of architecture simplifies
instruction decoding and is used in combination with
other techniques to increase parallelism.
4. Simple Instruction Formats. All instructions in
the 80960KB are 32 bits long and must be aligned on
word boundaries. This alignment makes it possible to
eliminate the instruction alignment stage in the
pipeline. To simplify the instruction decoder, there are
only five instruction formats; each instruction uses
only one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load
operations allow execution of subsequent instructions
to continue before the data has been returned from
memory, so that these instructions can overlap the
load. The 80960KB manages this process transpar-
ently to software through the use of a register score-
board. Conditional instructions also make use of a
scoreboard so that subsequent unrelated instructions
may be executed while the conditional instruction is
pending.
6. Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value is sent
immediately to its destination register. Yet at the same
time, the value is put on a bypass path to the ALU,
thereby saving the time that otherwise would be
required to retrieve the value for the next operation.
7. Bandwidth Optimizations. The 80960KB gets
optimal use of its memory bus bandwidth because the
bus is tuned for use with the on-chip instruction
cache: instruction cache line size matches the
maximum burst size for instruction fetches. The
80960KB automatically fetches four words in a burst
and stores them directly in the cache. Due to the size
of the cache and the fact that it is continually filled in
anticipation of needed instructions in the program
flow, the 80960KB is relatively insensitive to memory
wait states. The benefit is that the 80960KB delivers
outstanding performance even with a low cost
memory system.
8. Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then sends
it on to the instruction decoder at the same time it
updates the cache. Thus, no extra time is spent to
load and read the cache.
2