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80C186XL 80C188XL
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y Low Power Fully Static Versions of
80C186 80C188
Y Operation Modes
Enhanced Mode
DRAM Refresh Control Unit
Power-Save Mode
Direct Interface to 80C187
(80C186XL Only)
Compatible Mode
NMOS 80186 80188 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y Integrated Feature Set
Static Modular CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power-Save Mode
System-Level Testing Support (High
Impedance Test Mode)
Y Completely Object Code Compatible
with Existing 8086 8088 Software and
Has 10 Additional Instructions over
8086 8088
Y Speed Versions Available
25 MHz (80C186XL25 80C188XL25)
20 MHz (80C186XL20 80C188XL20)
12 MHz (80C186XL12 80C188XL12)
Y Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I O
Y Available in 68-Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier
(JEDEC A Package)
Y Available in 80-Pin
Quad Flat Pack (EIAJ)
Shrink Quad Flat Pack (SGFP)
Y Available in Extended Temperature
Range (b40 C to a85 C)
The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor It offers higher speed
and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com-
patibility Packaging and pinout are also identical
272431-1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272431-004
COPYRIGHT INTEL CORPORATION 1995
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80C186XL 80C188XL
16-Bit High-Integration Embedded Processors
CONTENTS
PAGE
INTRODUCTION
4
80C186XL CORE ARCHITECTURE
80C186XL Clock Generator
Bus Interface Unit
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5
80C186XL PERIPHERAL
ARCHITECTURE
Chip-Select Ready Generation Logic
DMA Unit
Timer Counter Unit
Interrupt Control Unit
Enhanced Mode Operation
Queue-Status Mode
DRAM Refresh Control Unit
Power-Save Control
Interface for 80C187 Math Coprocessor
(80C186XL Only)
ONCE Test Mode
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PACKAGE INFORMATION
Pin Descriptions
80C186XL 80C188XL Pinout
Diagrams
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8
16
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
22
22
DC SPECIFICATIONS
Power Supply Current
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23
CONTENTS
AC SPECIFICATIONS
Major Cycle Timings (Read Cycle)
Major Cycle Timings (Write Cycle)
Major Cycle Timings (Interrupt
Acknowledge Cycle)
Software Halt Cycle Timings
Clock Timings
Ready Peripheral and Queue Status
Timings
Reset and Hold HLDA Timings
AC TIMING WAVEFORMS
AC CHARACTERISTICS
EXPLANATION OF THE AC
SYMBOLS
DERATING CURVES
80C186XL 80C188XL EXPRESS
80C186XL 80C188XL EXECUTION
TIMINGS
INSTRUCTION SET SUMMARY
REVISION HISTORY
ERRATA
PRODUCT IDENTIFICATION
PAGE
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36
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80C186XL 80C188XL
NOTE
Pin names in parentheses applies to 80C188XL
Figure 1 80C186XL 80C188XL Block Diagram
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