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80C186EA 80C188EA AND 80L186EA 80L188EA
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y 80C186 Upgrade for Power Critical Applications
Y Fully Static Operation
Y True CMOS Inputs and Outputs
Y Integrated Feature Set
Static 186 CPU Core
Power Save Idle and Powerdown
Modes
Clock Generator
2 Independent DMA Channels
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
System-Level Testing Support
(High Impedance Test Mode)
Y Speed Versions Available (5V)
25 MHz (80C186EA25 80C188EA25)
20 MHz (80C186EA20 80C188EA20)
13 MHz (80C186EA13 80C188EA13)
Y Speed Versions Available (3V)
13 MHz (80L186EA13 80L188EA13)
8 MHz (80L186EA8 80L188EA8)
Y Direct Addressing Capability to
1 Mbyte Memory and 64 Kbyte I O
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EA only)
Y Available in the Following Packages
68-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin EIAJ Quad Flat Pack (QFP)
80-Pin Shrink Quad Flat Pack (SQFP)
Y Available in Extended Temperature
Range (b40 C to a85 C)
The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the
features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown
Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor
272432 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272432-003
COPYRIGHT INTEL CORPORATION 1995
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80C186EA 80C188EA 80L186EA 80L188EA
80C186EA 80C188EA AND 80L186EA 80L188EA
16-Bit High Integration Embedded Processor
CONTENTS
PAGE CONTENTS
PAGE
INTRODUCTION
80C186EA CORE ARCHITECTURE
Bus Interface Unit
Clock Generator
80C186EA PERIPHERAL
ARCHITECTURE
Interrupt Control Unit
Timer Counter Unit
DMA Control Unit
Chip-Select Unit
Refresh Control Unit
Power Management
80C187 Interface (80C186EA Only)
ONCE Test Mode
DIFFERENCES BETWEEN THE
80C186XL AND THE 80C186EA
Pinout Compatibility
Operating Modes
TTL vs CMOS Inputs
Timing Specifications
PACKAGE INFORMATION
Prefix Identification
Pin Descriptions
80C186EA Pinout
4 PACKAGE THERMAL
SPECIFICATIONS
4
4 ELECTRICAL SPECIFICATIONS
4 Absolute Maximum Ratings
Recommended Connections
5 DC SPECIFICATIONS
5 ICC versus Frequency and Voltage
5 PDTMR Pin Delay Calculation
7 AC SPECIFICATIONS
7 AC Characteristics 80C186EA20 13
7 AC Characteristics 80L186EA13 8
7 Relative Timings
8
8 AC TEST CONDITIONS
AC TIMING WAVEFORMS
8
DERATING CURVES
8
8 RESET
8 BUS CYCLE WAVEFORMS
8
EXECUTION TIMINGS
9
9 INSTRUCTION SET SUMMARY
9 REVISION HISTORY
15 ERRATA
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25
25
27
29
30
30
33
33
36
43
44
50
50
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80C186EA 80C188EA 80L186EA 80L188EA
NOTE
Pin names in parentheses apply to the 80C186EA 80L188EA
Figure 1 80C186EA 80C188EA Block Diagram
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