80C188EB.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 80C188EB 데이타시트 다운로드

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80C186EB 80C188EB AND 80L186EB 80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X Full Static Operation
X True CMOS Inputs and Outputs
Y Integrated Feature Set
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Speed Versions Available (5V)
25 MHz (80C186EB25 80C188EB25)
20 MHz (80C186EB20 80C188EB20)
13 MHz (80C186EB13 80C188EB13)
Y Available in Extended Temperature
Range (b40 C to a85 C)
Y Speed Versions Available (3V)
16 MHz (80L186EB16 80L188EB16)
13 MHz (80L186EB13 80L188EB13)
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y Available In
80-Pin Quad Flat Pack (QFP)
84-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new
to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent
Serial Channels I O ports and the capability of Idle or Powerdown low power modes
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Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
June, 2002
Order Number: 272433-005
COPYRIGHT © INTEL CORPORATION, 2002

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80C186EB 80C188EB and 80L186EB 80L188EB
16-Bit High-Integration Embedded Processors
CONTENTS
INTRODUCTION
CORE ARCHITECTURE
Bus Interface Unit
Clock Generator
80C186EC PERIPHERAL
ARCHITECTURE
Interrupt Control Unit
Timer Counter Unit
Serial Communications Unit
Chip-Select Unit
I O Port Unit
Refresh Control Unit
Power Management Unit
80C187 Interface (80C186EB Only)
ONCE Test Mode
PACKAGE INFORMATION
Prefix Identification
Pin Descriptions
80C186EB PINOUT
PACKAGE THERMAL
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PAGE
4
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4
4
5
5
5
7
7
7
7
7
7
7
8
8
8
14
22
23
23
CONTENTS
Recommended Connections
PAGE
23
DC SPECIFICATIONS
ICC versus Frequency and Voltage
PDTMR Pin Delay Calculation
24
27
27
AC SPECIFICATIONS
AC Characteristics 80C186EB25
AC Characteristics 80C186EB20 13
AC Characteristics 80L186EB16
Relative Timings
Serial Port Mode 0 Timings
28
28
30
32
36
37
AC TEST CONDITIONS
38
AC TIMING WAVEFORMS
38
DERATING CURVES
41
RESET
42
BUS CYCLE WAVEFORMS
45
EXECUTION TIMINGS
52
INSTRUCTION SET SUMMARY
53
ERRATA
59
REVISION HISTORY
59
2

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80C186EB 80C188EB 80L186EB 80L188EB
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
Figure 1 80C186EB 80C188EB Block Diagram
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