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® 80C286
January 28, 2008
High Performance Microprocessor
with Memory Management and Protection
Features
• Compatible with NMOS 80286
• Wide Range of Clock Rates
- DC to 25MHz (80C286-25)
- DC to 20MHz (80C286-20)
- DC to 16MHz (80C286-16)
- DC to 12.5MHz (80C286-12)
- DC to 10MHz (80C286-10)
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10)
220mA Maximum (80C286-12)
260mA Maximum (80C286-16)
310mA Maximum (80C286-20)
410mA Maximum (80C286-25)
• High Performance Processor (Up to 19 Times the 8086
Throughput)
• Large Address Space
• 16 Megabytes Physical/1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and Operat-
ing Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286 Real Address Mode
- PVAM
• Compatible with 80287 Numeric Data Co-Processor
• High Bandwidth Bus Interface (25 Megabyte/Sec)
• Available In
- 68 Pin PGA (Commercial, Industrial, and Military)
- 68 Pin PLCC (Commercial and Industrial)
Description
The Intersil 80C286 is a static CMOS version of the NMOS
80286 microprocessor. The 80C286 is an advanced, high-
performance microprocessor with specially optimized capa-
bilities for multiple user and multi-tasking systems. The
80C286 has built-in memory protection that supports operat-
ing system and task isolation as well as program and data
privacy within tasks. A 25MHz 80C286 provides up to nine-
teen times the throughput of a standard 5MHz 8086. The
80C286 includes memory management capabilities that map
230 (one gigabyte) of virtual address space per task into 224
bytes (16 megabytes) of physical memory.
The 80C286 is upwardly compatible with 80C86 and 80C88
software (the 80C286 instruction set is a superset of the
80C86/80C88 instruction set). Using the 80C286 real
address mode, the 80C286 is object code compatible with
existing 80C86 and 80C88 software. In protected virtual
address mode, the 80C286 is source code compatible with
80C86 and 80C88 software but may require upgrading to
use virtual address as supported by the 80C286’s integrated
memory management and protection mechanism. Both
modes operate at full 80C286 performance and execute a
superset of the 80C86 and 80C88 instructions.
The 80C286 provides special operations to support the effi-
cient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The 80C286 also supports virtual
memory systems by providing a segment-not-present excep-
tion and restartable instructions.
Ordering Information
PACKAGE
PGA
PLCC
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
0oC to +70oC
-40oC to +85oC
10MHz
-
IG80C286-10
5962-
9067801MXC
-
IS80C286-10
12.5MHz
CG80C286-12
IG80C286-12
5962-
9067802MXC
CS80C286-12
IS80C286-12
16MHz
CG80C286-16
-
-
CS80C286-16
IS80C286-16
20MHz
CG80C286-20
-
-
CS80C286-20
IS80C286-20
25MHz
-
-
-
CS80C286-25
-
PKG. NO.
G68.B
G68.B
G68.B
N68.95
N68.95
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
FN2947.3

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Pinouts
80C286
68 LEAD PGA
Component Pad View - As viewed from underside of the component when mounted on the board.
A0 D0
A2 A1
VCC
CLK
A3 RESET
A5 A4
A7 A6
A9 A8
A11 A10
A13 A12
35 37 39 41 43 45 47 49 51
34 36 38 40 42 44 46 48 50 53 52
32 33
55 54
30 31
57 56
28 29
59 58
26 27
61 60
24 25
63 62
22 23
65 64
20 21
67 66
18 19 16 14 12 10 8 6 4 2 68
17 15 13 11 9 7 5 3 1
ERROR NC
NC BUSY
INTR
NC
NMI NC
PEREQ
READY
HLDA
VSS
VCC
HOLD
M / IO
COD / INTA
NC LOCK
PIN 1 INDICATOR
68 LEAD PGA
P.C. Board View - As viewed from the component side of the P.C. board.
NC ERROR
BUSY
NC
NC INTR
NC NMI
VSS PEREQ
VCC READY
HOLD HLDA
COD / INTA
M / IO
LOCK
NC
51 49 47 45 43 41 39 37 35
52 53 50 48 46 44 42 40 38 36 34
54 55
33 32
56 57
31 30
58 59
29 28
60 61
27 26
62 63
25 24
64 65
23 22
66 67
21 20
68 2 4 6 8 10 12 14 16 19 18
1 3 5 7 9 11 13 15 17
D0 A0
A1 A2
CLK
VCC
RESET A3
A4 A5
A6 A7
A8 A9
A10 A11
A12 A13
PIN 1 INDICATOR
2

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Pinouts (Continued)
80C286
68 LEAD PLCC
P.C. Board View - As viewed from the component side of the P.C. board.
PIN 1 INDICATOR
BHE
NC
NC
S1
S0
PEACK
A23
A22
VSS
A21
A20
A19
A18
A17
A16
A15
A14
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1 51
2 50
3 49
4 48
5 47
6 46
7 45
8 44
9 43
10 42
11 41
12 40
13 39
14 38
15 37
16 36
17 35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
VSS
MOLD MARK DOES NOT
INDICATE PIN 1
Functional Diagram
ADDRESS UNIT (AU)
OFFSET
ADDER
SEGMENT
BASES
SEGMENT
LIMIT SEGMENT
CHECKER SIZES
PHYSICAL
ADDRESS
ADDER
ALU
ADDRESS
LATCHES AND DRIVERS
PRE-
FETCHER
PROCESSOR
EXTENSION
INTERFACE
BUS CONTROL
DATA TRANSCEIVERS
6-BYTE
PREFETCH
QUEUE
BUS UNIT (BU)
REGISTERS CONTROL
EXECUTION UNIT (EU)
3 DECODED
INSTRUCTION
QUEUE
INSTRUCTION
DECODER
INSTRUCTION
UNIT (IU)
NMI BUSY
INTR ERROR
A23 - A0,
BHE, M/IO
PEACK
PEREQ
READY,
HOLD,
S1, S0,
COD/INTA,
LOCK, HLDA
D15 - D0
RESET
CLK
VSS
VCC
3

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80C286
Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor.
SYMBOL
CLK
PIN
NUMBER
31
D15 - D0
36 - 51
A23 - A0
7-8
10 - 28
32 - 43
TYPE
I
I/O
O
DESCRIPTION
SYSTEM CLOCK: provides the fundamental timing for the 80C286 system. It is divided by two inside
the 80C286 to generate the processor clock. The internal divide-by-two circuitry can be synchro-
nized to an external clock generator by a LOW to HIGH transition on the RESET input.
DATA BUS: inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data
during memory and I/O write cycles. The data bus is active HIGH and is held at high impedance to
the last valid logic level during bus hold acknowledge.
ADDRESS BUS: outputs physical memory and I/O port addresses. A23 - A16 are LOW during I/O
transfers. A0 is LOW when data is to be transferred on pins D7 - D0 (see table below). The address
bus is active High and floats to three-state off during bus hold acknowledge.
BHE
1
O BUS HIGH ENABLE: indicates transfer of data on the upper byte of the data bus, D15 - D8. Eight-bit
oriented devices assigned to the upper byte of the data bus would normally use BHE to condition chip
select functions. BHE is active LOW and floats to three-state OFF during bus hold acknowledge.
BHE AND A0 ENCODINGS
BHE VALUE
0
A0 VALUE
0
Word transfer
FUNCTION
0 1 Byte transfer on upper half of data bus (D15 - D8)
1 0 Byte transfer on lower half of data bus (D7 - D0)
1 1 Reserved
S1, S0
4, 5
O BUS CYCLE STATUS: indicates initiation of a bus cycle and along with M/IO and COD/lNTA, de-
fines the type of bus cycle. The bus is in a TS state whenever one or both are LOW. S1 and S0 are
active LOW and are held at a high impedance logic one during bus hold acknowledge.
80C286 BUS CYCLE STATUS DEFINITION
COD/INTA M/IO
0(LOW)
0
00
00
00
01
01
01
01
1(HIGH)
0
10
10
10
11
11
11
11
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0 BUS CYCLE INITIATED
0 Interrupt acknowledge
1 Reserved
0 Reserved
1 None; not a status cycle
0 If A1 = 1 then halt; else shutdown
1 Memory data read
0 Memory data write
1 None; not a status cycle
0 Reserved
1 I/O read
0 I/O write
1 None; not a status cycle
0 Reserved
1 Memory instruction read
0 Reserved
1 None; not a status cycle
4

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80C286
Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor. (Continued)
PIN
SYMBOL NUMBER
TYPE
DESCRIPTION
M / IO
67
O MEMORY I/O SELECT: distinguishes memory access from I/O access. If HIGH during TS, a mem-
ory cycle or a halt/shutdown cycle is in progress. If LOW, an I/O cycle or an interrupt acknowledge
cycle is in progress. M/IO is held at high impedance to the last valid logic state during bus hold ac-
knowledge.
COD / lNTA
66
LOCK
68
O CODE/INTERRUPT ACKNOWLEDGE: distinguishes instruction fetch cycles from memory data
read cycles. Also distinguishes interrupt acknowledge cycles from I/O cycles. COD/lNTA is held at
high impedance to the last valid logic state during bus hold acknowledge. Its timing is the same as
M / IO.
O BUS LOCK: indicates that other system bus masters are not to gain control of the system bus for
the current and following bus cycles. The LOCK signal may be activated explicitly by the “LOCK”
instruction prefix or automatically by 80C286 hardware during memory XCHG instructions, interrupt
acknowledge, or descriptor table access. LOCK is active LOW and is held at a high impedance logic
one during bus hold acknowledge.
READY
63
HOLD
HLDA
64
65
INTR
57
NMI 59
PEREQ
PEACK
61
6
BUSY
ERROR
54
53
l BUS READY: terminates a bus cycle. Bus cycles are extended without limit until terminated by
READY LOW. READY is an active LOW synchronous input requiring setup and hold times relative
to the system clock be met for correct operation. READY is ignored during bus hold acknowledge.
(See Note 1)
I BUS HOLD REQUEST AND HOLD ACKNOWLEDGE: control ownership of the 80C286 local bus.
O The HOLD input allows another local bus master to request control of the local bus. When control is
granted, the 80C286 will float its bus drivers and then activate HLDA, thus entering the bus hold ac-
knowledge condition. The local bus will remain granted to the requesting master until HOLD be-
comes inactive which results in the 80C286 deactivating HLDA and regaining control of the local
bus. This terminates the bus hold acknowledge condition. HOLD may be asynchronous to the sys-
tem clock. These signals are active HIGH. Note that HLDA never floats.
I INTERRUPT REQUEST: requires the 80C286 to suspend its current program execution and service
a pending external request. Interrupt requests are masked whenever the interrupt enable bit in the
flag word is cleared. When the 80C286 responds to an interrupt request, it performs two interrupt
acknowledge bus cycles to read an 8-bit interrupt vector that identifies the source of the interrupt.
To ensure program interruption, INTR must remain active until an interrupt acknowledge bus cycle
is initiated. INTR is sampled at the beginning of each processor cycle and must be active HIGH at
least two processor cycles before the current instruction ends in order to interrupt before the next
instruction. INTR is level sensitive, active HIGH, and may be asynchronous to the system clock.
l NON-MASKABLE INTERRUPT REQUEST: interrupts the 80C286 with an internally supplied vector
value of two. No interrupt acknowledge cycles are performed. The interrupt enable bit in the 80C286
flag word does not affect this input. The NMI input is active HIGH, may be asynchronous to the sys-
tem clock, and is edge triggered after internal synchronization. For proper recognition, the input must
have been previously LOW for at least four system clock cycles and remain HIGH for at least four
system clock cycles.
l PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE: extend the memory
O management and protection capabilities of the 80C286 to processor extensions. The PEREQ input
requests the 80C286 to perform a data operand transfer for a processor extension. The PEACK out-
put signals the processor extension when the requested operand is being transferred. PEREQ is ac-
tive HIGH. PEACK is active LOW and is held at a high impedance logic one during bus hold
acknowledge. PEREQ may be asynchronous to the system clock.
l PROCESSOR EXTENSION BUSY AND ERROR: indicates the operating condition of a processor
I extension to the 80C286. An active BUSY input stops 80C286 program execution on WAIT and
some ESC instructions until BUSY becomes inactive (HIGH). The 80C286 may be interrupted while
waiting for BUSY to become inactive. An active ERROR input causes the 80C286 to perform a pro-
cessor extension interrupt when executing WAIT or some ESC instructions. These inputs are active
LOW and may be asynchronous to the system clock.
5