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87C51 80C51BH 80C31BH
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C51 80C51BH 80C51BHP 80C31BH
See Table 1 for Proliferation Options
Y High Performance CHMOS EPROM
Y 24 MHz Operation
Y Improved Quick-Pulse Programming
Algorithm
Y 3-Level Program Memory Lock
Y Boolean Processor
Y 128-Byte Data RAM
Y 32 Programmable I O Lines
Y Two 16-Bit Timer Counters
Y Extended Temperature Range
(b40 C to a85 C)
Y 5 Interrupt Sources
Y Programmable Serial Port
Y TTL- and CMOS-Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y ONCE Mode Facilitates System Testing
Y Power Control Modes
Idle
Power Down
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH) In
addition the device can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 128 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microcontroller which is fabricated on
Intel’s reliable CHMOS III-E technology Being a member of the MCS 51 controller family the
87C51 80C51BH 80C31BH uses the same powerful instruction set has the same architecture and is pin-for-
pin compatible with the existing MCS 51 controller family of products
The 80C51BHP is identical to the 80C51BH When ordering the 80C51BHP customers must submit the 64
byte encryption table together with the ROM code Lock bit 1 will be set to enable the internal ROM code
protection and at the same time allows code verification
The extremely low operating power along with the two reduced power modes Idle and Power Down make
this part very suitable for low power applications The Idle mode freezes the CPU while allowing the RAM
timer counters serial port and interrupt system to continue functioning The Power Down mode saves the
RAM contents but freezes the oscillator causing all other chip functions to be inoperative
For the remainder of this document the 87C51 80C51BH and 80C31BH will be referred to as the 87C51 BH
unless information applies to a specific device
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
October 1995
Order Number 272335-003

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87C51 80C51BH 80C31BH
80C31BH
80C51BH
80C51BHP
87C51
Table 1 Proliferation Options
Standard
-1
XX
XX
XX
XX
NOTES
3 5 MHz to 12 MHz VCC e 5V g20%
-1 3 5 MHz to 16 MHz VCC e 5V g20%
-2 0 5 MHz to 12 MHz VCC e 5V g20%
-24 3 5 MHz to 24 MHz VCC e 5V g20%
-2
X
X
X
X
-24
X
X
X
X
Figure 1 87C51 BH Block Diagram
272335 – 1
2

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87C51 80C51BH 80C31BH
PROCESS INFORMATION
The 87C51 BH is manufactured on the CHMOS III-E
process Additional process and reliability informa-
tion is available in Intel’s Components Quality and
Reliability Handbook Order No 210997
PACKAGES
Part
87C51 BH
Prefix
P
D
N
S
Package Type
40-Pin Plastic
DIP (OTP)
40-Pin CERDIP
(EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
DIP
272335 – 2
PLCC
272335 – 3
Do not connect reserved pins
QFP
Figure 2 Pin Connections
272335 – 4
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87C51 80C51BH 80C31BH
PIN DESCRIPTION
VCC Supply voltage during normal Idle and Power
Down operations
VSS Circuit ground
Port 0 Port 0 is an 8-bit open drain bidirectional I O
port As an output port each pin can sink several LS
TTL inputs Port 0 pins that have 1’s written to them
float and in that state can be used as high-imped-
ance inputs
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory In this
application it uses strong internal pullups when emit-
ting 1’s
Port 0 also receives the code bytes during EPROM
programming and outputs the code bytes during
program verification External pullups are required
during program verification
Port 1 Port 1 is an 8-bit bidirectional I O port with
internal pullups The Port 1 output buffers can drive
LS TTL inputs Port 1 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 1
pins that are externally pulled low will source current
(IIL on the data sheet) because of the internal pull-
ups
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion
Port 2 Port 2 is an 8-bit bidirectional I O port with
internal pullups Port 2 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 2
pins that are externally pulled low will source current
(IIL on the data sheet) because of the internal pull-
ups
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX DPTR) In this application it uses
strong internal pullups when emitting 1’s
During accesses to external Data Memory that use
8-bit addresses (MOVX Ri) Port 2 emits the con-
tents of the P2 Special Function Register
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification
Port 3 Port 3 is an 8-bit bidirectional I O port with
internal pullups The Port 3 output buffers can drive
LS TTL inputs Port 3 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally pulled low will source current
(IIL on the data sheet) because of the pullups
Port 3 also serves the functions of various special
features of the MCS-51 Family as listed below
Pin Name
Alternate Function
P3 0
P3 1
P3 2
P3 3
P3 4
P3 5
P3 6
P3 7
RXD
TXD
INT0
INT1
T0
T1
WR
RD
Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe
Port 3 also receives some control signals for
EPROM programming and program verification
RST Reset input A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice The port pins will be driven to their reset condi-
tion when a minimum VIH1 voltage is applied wheth-
er the oscillator is running or not An internal pull-
down resistor permits a power-on reset with only a
capacitor connected to VCC
ALE PROG Address Latch Enable output signal for
latching the low byte of the address during accesses
to external memory This pin is also the program
pulse input (PROG) during EPROM programming for
the 87C51
If desired ALE operation can be disabled by setting
bit 0 of SFR location 8EH With this bit set the pin is
weakly pulled high However the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction idle mode power down mode and ICE
mode The ALE disable feature will be terminated by
reset When the ALE disable feature is suspended or
terminated the ALE pin will no longer be pulled up
weakly Setting the ALE-disable bit has no effect if
the microcontroller is in external execution mode
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87C51 80C51BH 80C31BH
In normal operation ALE is emitted at a constant
rate of 1 6 the oscillator frequency and may be
used for external timing or clocking purposes Note
however that one ALE pulse is skipped during each
access to external Data Memory
PSEN Program Store Enable is the Read strobe to
External Program Memory When the 87C51 BH is
executing from Internal Program Memory PSEN is
inactive (high) When the device is executing code
from External Program Memory PSEN is activated
twice each machine cycle except that two PSEN
activations are skipped during each access to Exter-
nal Data Memory
EA VPP External Access enable EA must be
strapped to VSS in order to enable the 87C51 BH to
fetch code from External Program Memory locations
starting at 0000H up to FFFFH Note however that
if either of the Lock Bits is programmed the logic
level at EA is internally latched during reset
EA must be strapped to VCC for internal program
execution
This pin also receives the programming supply volt-
age (VPP) during EPROM programming
XTAL1 Input to the inverting oscillator amplifier
XTAL2 Output from the inverting oscillator amplifi-
er
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 4 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the data
sheet must be observed
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the VIL
and VIH specifications the capacitance will not ex-
ceed 20 pF
272335 – 6
Figure 4 External Clock Drive
272335 – 5
Figure 3 Using the On-Chip Oscillator
5