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INTEGRATED CIRCUITS
80C31X2/32X2
80C51X2/52X2/54X2/58X2
87C51X2/52X2/54X2/58X2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP
128B/256B RAM
low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
Preliminary data
2001 Sep 24
Philips
Semiconductors

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Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Preliminary data
80C3xX2; 80C5xX2;
87C5xX2
DESCRIPTION
The Philips microcontrollers described in this data sheet are
high-performance static 80C51 designs incorporating Philips’
high-density CMOS technology with operation from 2.7 V to 5.5 V.
They support both 6-clock and 12-clock operation.
The 8xC31X2/51X2 and 8xC32X2/52X2/54X2/58X2 contain
128 byte RAM and 256 byte RAM respectively, 32 I/O lines, three
16-bit counter/timers, a six-source, four-priority level nested interrupt
structure, a serial I/O port for either multi-processor
communications, I/O expansion or full duplex UART, and on-chip
oscillator and clock circuits.
In addition, the devices are low power static designs which offer a
wide range of operating frequencies down to zero. Two software
selectable modes of power reduction — idle mode and power-down
mode — are available. The idle mode freezes the CPU while
allowing the RAM, timers, serial port, and interrupt system to
continue functioning. The power-down mode saves the RAM
contents but freezes the oscillator, causing all other chip functions to
be inoperative. Since the design is static, the clock can be stopped
without loss of user data. Then the execution can be resumed from
the point the clock was stopped.
SELECTION TABLE
For applications requiring more ROM and RAM, as well as more
on-chip peripherals, see the P89C66x and P89C51Rx2 data sheets.
Type
Memory
Timers
Serial Interfaces
Max.
Freq.
at 6-clk
/ 12-clk
(MHz)
Freq.
Range
at 3V
(MHz)
Freq.
Range
at 5V
(MHz)
P87C58X2 256B – 32K – 3 – – – n – – – – 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P80C58X2 256B 32K –
– 3 – – –n– – –
– 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P87C54X2 256B – 16K – 3 – – – n – – – – 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P80C54X2 256B 16K –
– 3 – – –n– – –
– 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P87C52X2 256B – 8K – 3 – – – n – – – – 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P80C52X2 256B 8K –
– 3 – – –n– – –
– 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P87C51X2 128B – 4K – 3 – – – n – – – – 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P80C51X2 128B 4K –
– 3 – – –n– – –
– 32 6 (2) n 12–clk 6-clk 30/33 0–16 0–30/33
P80C32X2 256B – – – 3 – – – n – – – – 32 6 (2) – 12–clk 6-clk 30/33 0–16 0–30/33
P80C31X2 128B – – – 3 – – – n – – – – 32 6 (2) – 12–clk 6-clk 30/33 0–16 0–30/33
NOTE:
1. I2C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array;
ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation
2001 Sep 24
2

No Preview Available !

Philips Semiconductors
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
Preliminary data
80C3xX2; 80C5xX2;
87C5xX2
FEATURES
80C51 Central Processing Unit
4 kbytes ROM/EPROM (80/87C51X2)
8 kbytes ROM/EPROM (80/87C52X2)
16 kbytes ROM/EPROM (80/87C54X2)
32 kbytes ROM/EPROM (80/87C58X2)
128 byte RAM (80/87C51X2 and 80C31X2)
256 byte RAM (80/87C52/54X2/58X2 and 80C32X2)
Boolean processor
Fully static operation
Low voltage (2.7 V to 5.5 V at 16 MHz) operation
12-clock operation with selectable 6-clock operation
Memory addressing capability
64 kbytes ROM and 64 kbytes RAM
Power control modes:
Clock can be stopped and resumed
Idle mode
Power-down mode
CMOS and TTL compatible
Two speed ranges at VCC = 5 V
0 to 30 MHz with 6-clock operation
0 to 33 MHz with 12-clock operation
PLCC or DIP package (LQFP available soon)
Extended temperature ranges
Dual Data Pointers
Security bits:
ROM (2 bits)
OTP (3 bits)
Encryption array - 64 bytes
4 interrupt priority levels
6 interrupt sources
Four 8-bit I/O ports
Full-duplex enhanced UART
Framing error detection
Automatic address recognition
Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
Programmable clock-out
Asynchronous port reset
Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock
mode)
Wake-up from Power Down by an external interrupt.
2001 Sep 24
3