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Description
The MK1491-06 is a low cost, low jitter, high
performance clock synthesizer for National
Semiconductor CS5530 based computer and
portable appliance applications. Using patented
analog Phase-Locked Loop (PLL) techniques,
the device accepts a 14.318 MHz crystal input to
produce multiple output clocks. It provides
selectable PCI local bus and AC97 audio clocks,
24 MHz and 48 MHz clocks for Super I/O and
USB, as well as multiple Reference outputs.
The device has multiple power down modes to
reduce power consumption.
MK1491-06
CS5530 GeodeClock Source
Features
• Packaged in 28 pin, 300 mil wide SOIC or in
28 pin, 150 mil wide SSOP
• Provides all critical timing for the National
Semiconductor CS5530 Geode companion chip
• Four PCI clocks
• Selectable PCIF on up to 2 outputs
• Early PCI clock selectability
• Up to 4 Reference clocks
• 48 MHz USB and 24MHz SIO support
• AC97 audio clock
• Multiple power down modes
• Low EMI Enable pin reduces EMI radiation on
PCI clocks (patented)
• 3.3 V ±5% operation
Block Diagram
PCI Frequency Select
Low EMI Enable
PCIF Function Enable
Early PCI Enable
SLOW#
PCISTP#
PWRDWN#
Audio Select
VDD
6
2
14.3M/24M Select
XI
14.31818 MHz
crystal
XO
Crystal
Oscillator
GND
5
PCI
Clocks
Output
Buffers
Output
Buffer
3
PCI
EPCI/PCI
Audio
Clock
Fixed
Clocks
MUX
Output
Buffer
Output
Buffer
16.934 MHz or
24.576 MHz or
49.152 MHz
48 MHz
Output
Buffer
14.318 MHz or
24 MHz
Output
Buffers
3
14.318 MHz
MDS 1491-06 F
1 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

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MK1491-06
CS5530 GeodeClock Source
Pin Assignment
VDD
XI
XO
GND
14.3M(TS)
14.3M
GND
14.3M(SEL AUDIO)
VDD
SLOW#
GND
FS
SEL24
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Descriptions
PCI Frequency Select Table
28 AC97 AUDIO(PEN)
27 PCI
26 VDD
24M/14.3M Frequency
25 PCI
24 PCI
23 GND
22 PCI(EPCI#)
21 48M(LE#)
Select Table
SEL24 24M/14.3M
0 14.31818 MHz
1 24.0 MHz
20 VDD
19 24M/14.3M
PCIF Enable Control
18 VDD
PEN Pin 25 Pin 24
17 GND
0 PCI
PCI
16 PCISTP#
M PCI
PCIF
15 PWRDWN#
1 PCIF PCIF
PCIF continues to run in PCI STOP
mode. See table on page 4.
AC97 Audio Frequency Select
SEL AUDIO AC97 AUDIO
0 16.9344 MHz
M 24.576 MHz
1 49.152 MHz
TS
0
0
M
M
1
1
FS PCI
0 Tristate all clocks
1 Reserved
0 30 MHz
1 33.3 MHz
0 25 MHz
1 37.5 MHz
Early PCI Control Table
EPCI# PCI (Pin 22)
0 1 ns early
1 Normal
EMI Control
LE# PCI Low EMI
0 ON
1 OFF
Spread direction is DOWN..
Pin #
Name
Type Description
1, 9, 14
VDD
P Connect to +3.3V. Must be same voltage on all pins.
2 XI I Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
3 XO O Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
4, 7, 11, 17, 23
GND
P Connect to Ground.
5
14.3M(TS)
TI/O 14.318 MHz output. Input control for all clocks per table above.
6
14.3M
O 14.318 MHz buffered reference clock output.
8 14.3M(SEL AUDIO) TI/O 14.318 MHz output and audio frequency select input per table above.
10
SLOW#
I PCI normal or slow mode select input per table on page 4.
12 FS I Frequency Select for PCI clocks per table above.
13
SEL24
I Fixed frequency select input per table above. Selects frequency on pin 19.
15
PWRDWN#
I Power down control; defined in table on page 4.
16
PCISTP#
I PCI Stop power down control; defined in table on page 4.
18, 20, 26
VDD
P Connect to +3.3V. Must be same voltage on all pins.
19
24M/14.3M
O Fixed frequency clock output per table above.
21
48(LE#)
I/O Fixed frequency clock output and low EMI (spread spectrum) enable input per table above.
22
PCI(EPCI#)
I/O PCI Output clock that can be early. Input control for Early PCI per table above.
24 PCI O PCI Output clock. PCI/PCIF control set by PEN per table above.
25 PCI O PCI Output clock. PCI/PCIF control set by PEN per table above.
27 PCI O PCI Output clock.
28 AC97 AUDIO(PEN) TI/O Audio clock output and PCIF Function Enable per table above.
Key: I = Input, TI = tri-level input, O = Output, P = Power supply connection, (T)I/O = Input on power up, becomes an Output after 10ms.
Weak internal pull-up resistors are present on SEL24, EPCI#, FS, LE#, PCISTP#, and SLOW#. These pins should be tied to VDD or GND,
and not be left floating. Internal resistors on PEN, SEL AUDIO, and TS pull to a mid-level (M).
MDS 1491-06 F
2 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

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MK1491-06
CS5530 GeodeClock Source
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 2)
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
Ambient Operating Temperature
Soldering Temperature
Max of 10 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Mid-Level Voltage, VIM
Input Low Voltage, VIL
Output High Voltage, VOH
IOH=-8mA
Output Low Voltage, VOL
IOL=8mA
Output High Voltage, VOH
IOH=-8mA
Operating Supply Current, IDD
No Load, 33.3 MHz
Power Down mode Supply Current
Short Circuit Current, single output driver
VDD=3.3V
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle, all MHz clocks
At 1.5V
PCI Output to Output Skew
Rising edges at 1.5V
Skew of EPCI with respect to PCI
Cycle to Cycle Jitter, PCI clocks
EMI reduction, peaks of 5th - 19th odd harmonics 33.3 MHz PCI clock
Power up time, PWRDWN# high to all clocks stable
Power on time, applied VDD to all clocks stable
Minimum Typical Maximum Units
7V
-0.5 VDD+0.5 V
0 70 °C
260 °C
-65 150 °C
3.1 3.3
2
1.2 1.4
2.4
VDD-0.4
30
15
±60
7
3.45 V
V
1.6 V
0.8 V
V
0.4 V
V
mA
µΑ
mA
pF
14.31818
1.5
1.5
45 49 to 51 55
500
1
250
6 11
8 20
12 25
MHz
ns
ns
%
ps
ns
ps
dB
ms
ms
Note:
Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the
operating limits but below the Absolute Maximums may affect device reliability.
MDS 1491-06 F
3 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

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MK1491-06
CS5530 GeodeClock Source
Power Down Control Table
PCISTP# PWRDWN# SLOW#
X 0X
0 1X
1 1X
MODE
Power Down
PCI STOP
ON
PCI
LOW
LOW
ON
PCIF
LOW
ON
ON
24/14.3 14.3 DESCRIPTION
LOW LOW All outputs low. PLLs and Oscillator off.
ON ON PCI clocks synchronously enter and leave low state.
ON ON All Clocks On.
Key: 1 = connected to VDD, 0 = connected to ground, X = any valid logic level, Combination Input/Outputs should be connected to VDD or
Ground through a 10 kresistor as shown below.
Power-On Default Conditions
Input Pin#
5
8
10
12
13
15
16
21
22
28
Function
TS
SEL AUDIO
SLOW#
FS
SEL24
PWRDWN#
PCISTP#
LE#
EPCI#
PEN
Default Condition
M All outputs enabled.
M Audio clock (pin 28) set to 24.576 MHz
1 PCI clocks set to 33.3 MHz. Refer to Power Down Control Table above.
1 PCI frequency = 33.3 MHz.
1 24M/14.3M (pin 19) set to 24 MHz.
1 All clocks running.
1 PCI clocks running.
1 Low EMI function OFF
1 Pin 22 set to normal PCI signal (not early).
M PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
External Components
The MK1491-06 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be
connected on each VDD pin to ground, as close to the MK1491-06 as possible. A series termination resistor of 33may be used for
each clock output. See the discussion below for other external resistors required for proper I/O operation. The 14.3 MHz oscillator
has internal caps that provide the proper load for a parallel resonant crystal with CL=18 pF. For tuning with other values of CL, the
formula 2*(CL-18) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground.
I/O Structure
The MK1491-06 provides more functionality in a 28 pin package by using
a unique I/O technique. The device checks the status of all I/O pins
during power-up and at exit from the Power Down state. This status
(pulled high, low, or mid-level) then determines the frequency selections
and power down modes (see the tables on pages 2 and 4). Within 10ms
after power up, the inputs change to outputs and the clocks start up. In the
diagrams to the right, the 33resistors are the normal output
termination resistors. The 10kresistor pulls low to generate a logic
zero. Weak internal pull-up resistors are present on SEL24, EPCI#, FS,
LE#, PCISTP#, and SLOW#. These pins should be connected directly to
VDD or GND if not under active control. Internal resistors on PEN, SEL
AUDIO, and TS pull to a mid-level (M).
For select
= 0 (low)
33
I/O
to load*
10k
Don’t stuff for
“1” selection
*Note: Do not use a TTL load. This will
overcome the 10 kpulldown and force the
input to a logic 1.
MDS 1491-06 F
4 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

No Preview Available !

MK1491-06
CS5530 GeodeClock Source
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
INDEX
AREA
12
D
EH
h x 45°
A1
e
C
B
28 pin SOIC
Symbol
A
A1
B
C
D
E
e
H
h
L
Inches
Min Max
-- 0.104
0.0040 --
0.013 0.020
0.007 0.013
0.697 0.724
0.291 0.299
.050 BSC
0.394 0.419
0.01 0.029
0.016 0.050
Millimeters
Min Max
-- 2.65
0.10 --
0.33 0.51
0.18 0.33
17.70 18.39
7.40 7.60
1.27 BSC
10.01 10.64
0.25 0.74
0.41 1.27
A
L
MDS 1491-06 F
5 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com