CS5530 Geode™ Clock Source
Power Down Control Table
PCISTP# PWRDWN# SLOW#
24/14.3 14.3 DESCRIPTION
LOW LOW All outputs low. PLLs and Oscillator off.
ON ON PCI clocks synchronously enter and leave low state.
ON ON All Clocks On.
Key: 1 = connected to VDD, 0 = connected to ground, X = any valid logic level, Combination Input/Outputs should be connected to VDD or
Ground through a 10 kΩ resistor as shown below.
Power-On Default Conditions
M All outputs enabled.
M Audio clock (pin 28) set to 24.576 MHz
1 PCI clocks set to 33.3 MHz. Refer to Power Down Control Table above.
1 PCI frequency = 33.3 MHz.
1 24M/14.3M (pin 19) set to 24 MHz.
1 All clocks running.
1 PCI clocks running.
1 Low EMI function OFF
1 Pin 22 set to normal PCI signal (not early).
M PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
The MK1491-06 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be
connected on each VDD pin to ground, as close to the MK1491-06 as possible. A series termination resistor of 33Ω may be used for
each clock output. See the discussion below for other external resistors required for proper I/O operation. The 14.3 MHz oscillator
has internal caps that provide the proper load for a parallel resonant crystal with CL=18 pF. For tuning with other values of CL, the
formula 2*(CL-18) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground.
The MK1491-06 provides more functionality in a 28 pin package by using
a unique I/O technique. The device checks the status of all I/O pins
during power-up and at exit from the Power Down state. This status
(pulled high, low, or mid-level) then determines the frequency selections
and power down modes (see the tables on pages 2 and 4). Within 10ms
after power up, the inputs change to outputs and the clocks start up. In the
diagrams to the right, the 33Ω resistors are the normal output
termination resistors. The 10kΩ resistor pulls low to generate a logic
zero. Weak internal pull-up resistors are present on SEL24, EPCI#, FS,
LE#, PCISTP#, and SLOW#. These pins should be connected directly to
VDD or GND if not under active control. Internal resistors on PEN, SEL
AUDIO, and TS pull to a mid-level (M).
= 0 (low)
Don’t stuff for
*Note: Do not use a TTL load. This will
overcome the 10 kΩ pulldown and force the
input to a logic 1.
MDS 1491-06 F
4 Revision 101700 Printed 11/15/00
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