80C550.pdf 데이터시트 (총 28 페이지) - 파일 다운로드 80C550 데이타시트 다운로드

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INTEGRATED CIRCUITS
80C550/83C550/87C550
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D,
watchdog timer
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors

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Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Product specification
80C550/83C550/87C550
DESCRIPTION
The Philips 8XC550 is a high-performance microcontroller fabricated
with Philips high-density CMOS technology. This Philips CMOS
technology combines the high speed and density characteristics of
HMOS with the low power attributes of CMOS. Philips epitaxial
substrate minimizes latch-up sensitivity. The CMOS 8XC550 has the
same instruction set as the 80C51.
The 8XC550 contains a 4k × 8 EPROM (87C550)/ROM
(83C550)/ROMless (80C550 has no program memory on-chip), a
128 × 8 RAM, 8 channels of 8-bit A/D, four 8-bit ports (port 1 is input
only), a watchdog timer, two 16-bit counter/timers, a seven-source,
two-priority level nested interrupt structure, a serial I/O port for either
multi-processor communications, I/O expansion or full duplex UART,
and an on-chip oscillator and clock circuits.
In addition, the 8XC550 has two software selectable modes of
power reduction—idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
FEATURES
80C51 based architecture
– 4k × 8 EPROM (87C550)/ROM (83C550)
– 128 × 8 RAM
– Eight channels of 8-bit A/D
– Two 16-bit counter/timers
– Watchdog timer
– Full duplex serial channel
– Boolean processor
Memory addressing capability
– 64k ROM and 64k RAM
Power control modes:
– Idle mode
– Power-down mode
CMOS and TTL compatible
One speed range at VCC = 5V ±10%
– 3.5 to 16MHz
Extended temperature ranges
OTP package available
ORDERING INFORMATION
ROMless
ROM
EPROM
P80C550EBP N P83C550EBP N P87C550EBP N
P80C550EBA A P83C550EBA A P87C550EBA A
P80C550EFA A P83C550EFA A P87C550EFA A
NOTES:
1. OTP = One Time Programmable EPROM.
OTP
OTP
OTP
TEMPERATURE RANGE °C
AND PACKAGE 1
0 to +70, Plastic Dual In-Line Package
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Leaded Chip Carrier
FREQ
MHz
3.5 to 16
3.5 to 16
3.5 to 16
DRAWING
NUMBER
SOT129-1
SOT187-2
SOT187-2
1998 May 01
2 853-1568 19329

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Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Product specification
80C550/83C550/87C550
BLOCK DIAGRAM
VCC
VSS
RAM ADDR
REGISTER
RAM
P0.0–P0.7
PORT 0
DRIVERS
PORT 0
LATCH
P2.0–P2.7
PORT 2
DRIVERS
PORT 2
LATCH
ROM/EPROM
B
REGISTER
ACC
TMP2
TMP1
STACK
POINTER
ALU
PSW
PCON
TL1
SCON TMOD TCON
TH0 TL0 TH1
SBUF IE
IP
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PSEN
ALE/PROG
EA/VPP
RST
TIMING
AND
CONTROL
PD
OSCILLATOR
XTAL1
XTAL2
PORT 1
LATCH
PORT 1
DRIVERS
P1.0–P1.7
PORT 3
LATCH
PORT 3
DRIVERS
P3.0–P3.7
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
PROGRAM
COUNTER
DPTR
SU00005
1998 May 01
3

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Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
PIN CONFIGURATIONS
AVCC/Vref+ 1
AVSS/Vref– 2
P1.0/ADC0 3
40 VCC
39 P0.0/AD0
38 P0.1/AD1
P1.1/ADC1 4
37 P0.2/AD2
P1.2/ADC2 5
36 P0.3/AD3
P1.3/ADC3 6
35 P0.4/AD4
P1.4/ADC4 7
34 P0.5/AD5
P1.5/ADC5 8
33 P0.6/AD6
RST 9
RxD/P3.0 10
TxD/P3.1 11
PLASTIC
DUAL
IN-LINE
PACKAGE
32 P0.7/AD7
31 EA/VPP
30 ALE/PROG
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
6 1 40
7 39
PLASTIC
LEADED
CHIP CARRIER
17 29
18 28
Pin Function
1 AVCC
2 Vref+
3 Vref–
4 AVSS
5 P1.0/ADC0
6 P1.1/ADC1
7 P1.2/ADC2
8 P1.3/ADC3
9 P1.4/ADC4
10 P1.5/ADC5
11 P1.6/ADC6
12 P1.7/ADC7
13 RST
14 P3.0/RxD
15 P3.1/TxD
Pin Function
16 P3.2/INT0
17 P3.3/INT1
18 P3.4/T0
19 P3.5/T1
20 P3.6/WR
21 P3.7/RD
22 XTAL2
23 XTAL1
24 VSS
25 P2.0/A8
26 P2.1/A9
27 P2.2/A10
28 P2.3/A11
29 P2.4/A12
30 P2.5/A13
Pin Function
31 P2.6/A14
32 P2.7/A15
33 PSEN
34 ALE/PROG
35 EA/VPP
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 VCC
SU00196
Product specification
80C550/83C550/87C550
1998 May 01
4

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Philips Semiconductors
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
Product specification
80C550/83C550/87C550
PIN DESCRIPTION
MNEMONIC
PIN NO.
DIP LCC TYPE
NAME AND FUNCTION
VSS
VCC
AVCC
AVSS
Vref+
Vref–
P0.0–0.7
20 24
I Ground: 0V reference.
40 44
I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
1 1 I Analog Power Supply: Analog supply voltage.
2 4 I Analog Ground: Analog 0V reference.
2 I Vref: A/D converter reference level inputs. Note that these references are combined with AVCC and
3 I AVSS in the 40-pin DIP package.
39–32 43–36 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory. In this application, it uses strong
internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in
the S87C550. External pull-ups are required during program verification.
P1.0–P1.7
3–8 5–12
I Port 1: Port 1 is an 8-bit input only port (6-bit in the DIP package; bits P1.6 and P1.7 are not
implemented). Port 1 digital input can be read out any time.
ADC0–ADC7 3–8 5–12
ADCx: Inputs to the analog multiplexer input of the 8-bit A/D. There are only six A/D inputs in the
DIP package.
P2.0–P2.7
21–28 25–32 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that
are externally being pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register.
P3.0–P3.7
RST
ALE/PROG
10–17 14–21 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that
are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below:
10 14
I RxD (P3.0): Serial input port
11 15 O TxD (P3.1): Serial output port
12 16
I INT0 (P3.2): External interrupt
13 17
I INT1 (P3.3): External interrupt
14 18
I T0 (P3.4): Timer 0 external input
15 19
I T1 (P3.5): Timer 1 external input
16 20 O WR (P3.6): External data memory write strobe
17 21 O RD (P3.7): External data memory read strobe
9 13 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to
VCC.
30 34 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program pulse input
(PROG) during EPROM programming.
PSEN
29 33 O Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.
EA/VPP
31 35
I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable
the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held
high, the device executes from internal program memory unless the program counter contains an
address greater than 0FFFH. For the 80C550 ROMless part, EA must be held low for the part to
operate properly. This pin also receives the 12.75V programming supply voltage (VPP) during
EPROM programming.
XTAL1
19 23
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
XTAL2
18 22 O Crystal 2: Output from the inverting oscillator amplifier.
1998 May 01
5