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INTEGRATED CIRCUITS
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C,
PWM, capture/compare, high I/O, 64L LQFP
Preliminary specification
Replaces data of 1999 Apr 07
IC20 Data Handbook
2000 Nov 10
Philips
Semiconductors

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Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
DESCRIPTION
This data sheet describes the 6 clock version of the 8xC554. This
device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit
Microcontroller is manufactured in an advanced CMOS process and
is a derivative of the 80C51 microcontroller family. The 87C554 has
the same instruction set as the 80C51. Three versions of the
derivative exist:
83C554—16k bytes ROM
80C554—ROMless version
87C554—16k bytes EPROM
The 87C554 contains a 16k × 8 non-volatile EPROM, a 512 × 8
read/write data memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, four-priority-level, nested interrupt structure, an 7-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I2C-bus), a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that require extra
capability, the 8xC554 can be expanded using standard TTL
compatible memories and logic.
In addition, the 8xC554 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. Optionally, the ADC can be operated
in Idle mode. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-byte. With an 8 MHz crystal,
58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs.
Multiply and divide instructions require 3 µs.
FEATURES
80C51 central processing unit
16k × 8 EPROM expandable externally to 64k bytes
An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
Two standard 16-bit timer/counters
512 × 8 RAM, expandable externally to 64k bytes
Capable of producing eight synchronized, timed outputs
A 10-bit ADC with seven multiplexed analog inputs
Fast 8-bit ADC option – 9 µS at 16 MHz
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I2C-bus serial I/O port with byte oriented master and slave
functions
On-chip watchdog timer
Extended temperature ranges
Full static operation – 0 to 16 MHz
Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and
4.5 V to 5.5 V (8 to 16 MHz) commercial temperature
Security bits:
– ROM – 2 bits
– OTP/EPROM – 3 bits
4 level priority interrupt
15 interrupt sources
Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
Power control modes
– Clock can be stopped and resumed
– Idle mode
– Power down mode
Second DPTR register
EMI reduction – 6 clock operation and ALE inhibit
Programmable I/O pins
Wake-up from power-down by external interrupts
Software reset
Power-on detect reset
ADC charge pump disable
ONCE mode
ADC active in Idle mode
2000 Nov 10
2

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Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
ORDERING INFORMATION
OTP/EPROM
ROM
P87C554SBBD
P83C554SBBD
P87C554SFBD
P83C554SFBD
ROMless
P80C554SBBD
P80C554SFBD
TEMPERATURE °C AND PACKAGE
0 to +70, Low Profile Quad Flat Package
–40 to +85, Low Profile Quad Flat
Package
FREQ.
(MHz)
16
16
DRAWING
NUMBER
SOT314–2
SOT314–2
PART NUMBER DERIVATION
DEVICE NUMBER
OPERATING FREQUENCY MAX
P87C554 OTP
P83C554 ROM
S = 16 MHz
P80C554 ROMless
TEMPERATURE RANGE
B= 0_C to 70_C
F = –40_C to +85_C
PACKAGE
BD=64L LQFP
BLOCK DIAGRAM
T0 T1
33
INT0 INT1
33
VDD
VSS
PWM0
PWM1
AVSS AVREF ADC0-7 SDA SCL
–+
AVDD STADC
51 1
XTAL1
XTAL2
EA
ALE
PSEN
3
WR
3
RD
0
AD0-7
2
A8-15
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
80C51 CORE
EXCLUDING
ROM/RAM
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
PROGRAM
MEMORY
16k x 8
OTP/ROM
DATA
MEMORY
512 x 8 RAM
DUAL
PWM
ADC
SERIAL
I2C PORT
8-BIT INTERNAL BUS
16
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
T2
16-BIT
TIMER/
EVENT
COUNTERS
16
T2
16-BIT
COMPARA-
TORS
WITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
33
P0 P1 P2 P3 TxD RxD
P5 P4
1
CT0I-CT3I
1
T2
1
RT2
0 ALTERNATE FUNCTION OF PORT 0
1 ALTERNATE FUNCTION OF PORT 1
2 ALTERNATE FUNCTION OF PORT 2
3 ALTERNATE FUNCTION OF PORT 3
4 ALTERNATE FUNCTION OF PORT 4
5 ALTERNATE FUNCTION OF PORT 5
4
CMSR0-CMSR5 RST EW
CMT0, CMT1
SU00951
2000 Nov 10
3

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Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
PIN CONFIGURATIONS
Plastic Quad Flat Pack pin functions
48 33
49
LQFP64
64
32
17
1 16
Pin Function
1. AVDD
2. P5.6/ADC6
3. P5.5/ADC5
4. P5.4/ADC4
5. P5.3/ADC3
6. P5.2/ADC2
7. P5.1/ADC1
8. P5.0/ADC0
9. VDD
10. STADC
11. PWM0
12. PWM1
13. EW
14. P4.0/CMSR0
15. P4.1/CMSR1
16. P4.2/CMSR2
Pin Function
17. P4.3/CMSR3
18. P4.4/CMSR4
19. P4.5/CMSR5
20. P4.6/CMT0
21. P4.7/CMT1
22. RST
23. P1.0/CT0I
24. P1.1/CT1I
25. P1.2/CT2I
26. P1.3/CT3I
27. P1.4/T2
28. P1.5/RT2
29. P1.6/SCL
30. P1.7/SDA
31. P3.0/RxD
32. P3.1/TxD
Pin Function
33. P3.2/INT0
34. P3.3/INT1
35. P3.4/T0
36. P3.5/T1
37. P3.6/WR
38. P3.7/RD
39. XTAL2
40. XTAL1
41. VSS
42. VSS
43. P2.0/A08
44. P2.1/A09
45. P2.2/A10
46. P2.3/A11
47. P2.4/A12
48. P2.5/A13
LOGIC SYMBOL
VSS
VDD
XTAL1
XTAL2
EA/VPP
ALE/PROG
PSEN
AVSS
AVDD
AVref+
AVref–
STADC
PWM0
PWM1
ADC0-7
CMSR0-5
CMT0
CMT1
RST
EW
LOW ORDER
ADDRESS AND
DATA BUS
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
HIGH ORDER
ADDRESS AND
DATA BUS
RxD/DATA
TxD/CLOCK
INT0
INT1
T0
T1
WR
RD
SU00210
Pin Function
49. P2.6/A14
50. P2.7/A15
51. PSEN
52. ALE/PROG
53. EA/VPP
54. P0.7/AD7
55. P0.6/AD6
56. P0.5/AD5
57. P0.4/AD4
58. P0.3/AD3
59. P0.2/AD2
60. P0.1/AD1
61. P0.0/AD0
62. AVref–
63. AVref+
64. AVSS
SU01444
2000 Nov 10
4

No Preview Available !

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
PIN DESCRIPTION
PIN NO.
MNEMONIC
LQFP
VDD
9
STADC
10
PWM0
PWM1
EW
P0.0-P0.7
11
12
13
54–61
P1.0-P1.7
23–30
23–28
29–30
23–26
27
28
29
30
P2.0-P2.7
43–50
P3.0-P3.7
31–38
31
32
33
34
35
36
37
38
TYPE
I
I
O
O
I
I/O
I/O
I/O
I/O
I
I
I
I/O
I/O
I/O
I/O
NAME AND FUNCTION
Digital Power Supply: Positive voltage power supply pin during normal operation, idle and
power-down mode.
Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be
started by software).
Pulse Width Modulation: Output 0.
Pulse Width Modulation: Output 1.
Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application it uses
strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during
programming and to output the code byte during verification.
Port 1: 8-bit I/O port. Alternate functions include:
(P1.0-P1.5): Programmable I/O port pins.
(P1.6, P1.7): Open drain port pins.
CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
T2 (P1.4): T2 event input.
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
SCL (P1.6): Serial port clock line I2C-bus.
SDA (P1.7): Serial port data line I2C-bus.
Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as
follows:
P1M1.x
0
0
1
1
P1M2.x
0
1
0
1
Mode Description
Pseudo–bidirectional (standard c51 configuration; default)
Push-Pull
High impedance
Open drain
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
Port 2: 8-bit programmable I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to
input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on
P2.1, through A13 on P2.5.
Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers
as follows:
P2M1.x
0
0
1
1
P2M2.x
0
1
0
1
Mode Description
Pseudo–bidirectional (standard c51 configuration; default)
Push-Pull
High impedance
Open drain
Port 3: 8-bit programmable I/O port. Alternate functions include:
RxD(P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt.
INT1 (P3.3): External interrupt.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as
follows:
P3M1.x
0
0
1
1
P3M2.x
0
1
0
1
Mode Description
Pseudo–bidirectional (standard c51 configuration; default)
Push–Pull
High impedance
Open drain
2000 Nov 10
5