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INTEGRATED CIRCUITS
80C575/83C575/87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator,
failure detect circuitry, watchdog timer
Product specification
Supersedes data of 1998 Jan 27
IC20 Data Handbook
1998 May 01
Philips
Semiconductors

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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
DESCRIPTION
The Philips 80C575/83C575/87C575 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The Philips CMOS technology combines the
high speed and density characteristics of
HMOS with the low power attributes of
CMOS. Philips epitaxial substrate minimizes
latch-up sensitivity.
The 8XC575 contains an 8k × 8 ROM
(83C575) EPROM (87C575), a 256 × 8 RAM,
32 I/O lines, three 16-bit counter/timers, a
Programmable Counter Array (PCA), a
seven-source, two-priority level nested
interrupt structure, an enhanced UART, four
analog comparators, power-fail detect and
oscillator fail detect circuits, and on-chip
oscillator and clock circuits.
In addition, the 8XC575 has a low active
reset, and the port pins are reset to a low
level. There is also a fully configurable
watchdog timer, and internal power on clear
circuit. The part includes idle mode and
power-down mode states for reduced power
consumption.
FEATURES
80C51 based architecture
8k × 8 ROM (83C575)
8k × 8 EPROM (87C575)
ROMless (80C575)
256 × 8 RAM
Three 16-bit counter/timers
Programmable Counter Array
Enhanced UART
Boolean processor
Oscillator fail detect
Low active reset
Asynchronous low port reset
Schmitt trigger inputs
4 analog comparators
Watchdog timer
Low VCC detect
Memory addressing capability
64k ROM and 64k RAM
Power control modes:
Idle mode
Power-down mode
CMOS and TTL compatible
4.0 to 16MHz
Extended temperature ranges
OTP package available
PIN CONFIGURATIONS
CMP0+/P1.0/T2 1
CMP0-/P1.1/T2EX 2
40 VDD
39 P0.0/AD0
ECI/P1.2 3
38 P0.1/AD1
CMP0/CEX0/P1.3 4
37 P0.2/AD2
CMP1/CEX1/P1.4 5
36 P0.3/AD3
CMP2/CEX2/P1.5 6
35 P0.4/AD4
CMP3/CEX3/P1.6 7
34 P0.5/AD5
CEX4/P1.7 8
33 P0.6/AD6
RST 9
32 P0.7/AD7
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
DUAL
IN-LINE
PACKAGE
31 EA/VPP
30 ALE/PROG
29 PSEN
INT1/P3.3 13
28 P2.7/A15
CMPR-/T0/P3.4 14
27 P2.6/A14
CMP1+/T1/P3.5 15
26 P2.5/A13
CMP2+/WR/P3.6 16
25 P2.4/A12
CMP3+/RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
6 1 40
7 39 1
17 LCC
29 11
18 28
44 34
PQFP
33
23
12 22
SU00234
ORDERING INFORMATION
ROMless
ROM
EPROM1
P80C575EBP N P83C575EBP N P87C575EBPN
P80C575EBA A P83C575EBA A P87C575EBAA
P80C575EHAA P83C575EHAA P87C575EHAA
P80C575EBB B P83C575EBB B P87C575EBBB
NOTE:
1. OTP - One Time Programmable EPROM.
OTP
OTP
OTP
OTP
TEMPERATURE RANGE °C AND PACKAGE
0 to +70, 40-Pin Plastic Dual In-line Package
0 to +70, 44-Pin Plastic Leaded Chip Carrier
–40 to +125, 44-Pin Plastic Leaded Chip Carrier
0 to +70, 44-Pin Plastic Quad Flat Pack
FREQ DRAWING
(MHz) NUMBER
16 SOT129-1
16 SOT187-2
16 SOT187-2
16 SOT307-2
1998 May 01
2 853-1684 19332

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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
BLOCK DIAGRAM
VCC
VSS
RAM ADDR
REGISTER
RAM
P0.0-P0.7
PORT 0
DRIVERS
PORT 0
LATCH
P2.0-P2.7
PORT 2
DRIVERS
PORT 2
LATCH
ROM/
EPROM
B
REGISTER
ACC
TMP2
TMP1
STACK
POINTER
ALU
PSW
SFRs
TIMERS
PCA
PSEN
ALE
EA
RST
TIMING
AND
CONTROL
PD
OSCILLATOR
XTAL1
XTAL2
PORT 1
LATCH
PORT 1
DRIVERS
P1.0-P1.7
PORT 3
LATCH
PORT 3
DRIVERS
P3.0-P3.7
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
PROGRAM
COUNTER
DPTR
SU00238
1998 May 01
3

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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
CERAMIC AND PLASTIC LEADED PLASTIC QUAD FLAT PACK
CHIP CARRIER PIN FUNCTIONS PIN FUNCTIONS
6 1 40
44 34
7 39
LCC
1 33
PQFP
17 29 11
23
18 28
Pin Function
1 NC*
2 T2/P1.0/CMP0+
3 T2EX/P1.1/CMP0–
4 P1.2/ECI
5 P1.3/CMP0/CEX0
6 P1.4/CMP1/CEX1
7 P1.5/CMP2/CEX2
8 P1.6/CMP3/CEX3
9 P1.7/CEX4
10 RST
11 RxD/P3.0
12 NC*
13 TxD/P3.1
14 INT0/P3.2
15 INT1/P3.3
16 T0/P3.4/CMPR–
17 T1/P3.5/CMP1+
18 WR/P3.6/CMP2+
19 RD/P3.7/CMP3+
20 XTAL2
21 XTAL1
22 VSS
Pin Function
23 NC*
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
31 P2.7/A15
32 PSEN
33 ALE/PROG
34 NC*
35 EA/VPP
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 VCC
* NO INTERNAL CONNECTION
SU00235
12
Pin Function
1 P1.5/CMP2/CEX2
2 P1.6/CMP3/CEX3
3 P1.7/CEX4
4 RST
5 RxD/P3.0
6 NC*
7 TxD/P3.1
8 INT0/P3.2
9 INT1/P3.3
10 T0/P3.4/CMPR–
11 T1/P3.5/CMP1+
12 WR/P3.6/CMP2+
13 RD/P3.7CMP3+
14 XTAL2
15 XTAL1
16 VSS
17 NC*
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12
22
Pin Function
23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE/PROG
28 NC*
29 EA/VPP
30 P0.7/AD7
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 VCC
39 NC*
40 T2/P1.0/CMP0+
41 T2EX/P1.1/CMP0–
42 P1.2/ECI
43 P1.3/CMP0/CEX0
44 P1.4/CMP1/CEX1
* NO INTERNAL CONNECTION
SU00236
LOGIC SYMBOL
VCC VSS
XTAL1
CMPR–
CMP1+
CMP2+
CMP3+
XTAL2
RST
EA/VPP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS AND
DATA BUS
T2
T2EX
CMP0+
CMP0–
ECI
CMP0/CEX0
CMP1/CEX1
CMP2/CEX2
CMP3/CEX3
CEX4
ADDRESS BUS
SU00237
1998 May 01
4
Product specification
80C575/83C575/
87C575

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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
VSS
20 22 16
I Ground: 0V reference.
VCC
40 44 38
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0-0.7
P1.0-P1.7
39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code
bytes during EPROM programming and outputs code bytes during program verification.
External pull-ups are required during program verification. During reset, port 0 will be
asynchronously driven low and will remain low until written to by software. All port 0 pins
have Schmitt trigger inputs with 200mV hysteresis. A weak pulldown on port 0 guarantees
positive leakage current (see DC Electrical Characteristics: IL1).
1-8 2-9 40-44 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port. Port 1 pins have internal pull-ups such that
1-3 pins that have 1s written to them can be used as inputs but will source current when
externally pulled low (see DC Electrical Characteristics: IIL). Port 1 receives the low-order
address byte during program memory verification and EPROM programming. During reset,
port 1 will be asynchronously driven low and will remain low until written to by software. All
port 1 pins have Schmitt trigger inputs with 50mV hysteresis. Port 1 pins also serve
alternate functions as follows:
1 2 40 I/O P1.0 T2 Timer 2 external I/O – clockout (programmable)
CMP0+ Comparator 0 positive input
2 3 41 I P1.1 T2EX Timer 2 capture input
CMP0- Comparator 0 negative input
3
4 42
I P1.2 ECI
PCA count input
4 5 43 I/O P1.3 CEX0 PCA module 0 external I/O
CMP0 Comparator 0 output
5 6 44 I/O P1.4 CEX1 PCA module 1 external I/O
CMP1 Comparator 1 output
6 7 1 I/O P1.5 CEX2 PCA module 2 external I/O
CMP2 Comparator 2 output
7 8 2 I/O P1.6 CEX3 PCA module 3 external I/O
CMP3 Comparator 3 output
8 9 3 I/O P1.7 CEX4 PCA module 4 external I/O
P2.0-P2.7
P3.0-P3.7
21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them can be used as inputs, but will source current when externally pulled low
(see DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during
accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Port 2
receives the high-order address byte during program verification and EPROM programming.
During reset, port 2 will be asynchronously driven low and will remain low until written to by
software. Port 2 can be made open drain by writing to the P2OD register (AIH). In open
drain mode, weak pulldowns on port 2 guarantee positive leakage current (see DC
Electrical Characteristics IL1).
10-17 11,
5,
13-19 7-13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins except P3.1
that have 1s written to them can be used as inputs but will source current when externally
pulled low (see DC Electrical Characteristics: IIL). P3.1 will be a high impedance pin except
while transmitting serial data, in which case the strong pull-up will remain on continuously
when outputting a 1 level. The P3.1 output drive level when transmitting can be set to one of
two levels by the writing to the P3.1 register bit. During reset all pins (except P3.1) will be
asynchronously driven low and will remain low until written to by software. All port 3 pins
have Schmitt trigger inputs with 200mV hysteresis, except P3.2 and P3.3, which have 50mV
hysteresis. Port 3 pins serve alternate functions as follows:
1998 May 01
5