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INTEGRATED CIRCUITS
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
Supersedes data of 1992 Nov 25
IC20 Data Handbook
1998 Jul 03
Philips
Semiconductors

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Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
80C851/83C851
DESCRIPTION
The Philips 80C851/83C851 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The 80C851/83C851 has the same
instruction set as the 80C51. The Philips
CMOS technology combines the high speed
and density characteristics of HMOS with the
low power attributes of CMOS. The Philips
epitaxial substrate minimizes latch-up
sensitivity.
The 80C851/83C851 contains a 4k × 8 ROM
with mask-programmable ROM code
protection, a 128 × 8 RAM, 256 × 8
EEPROM, 32 I/O lines, two 16-bit
counter/timers, a seven-source, five vector,
two-priority level nested interrupt structure,
a serial I/O port for either multi-processor
communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock
circuits.
In addition, the 80C851/83C851 has two
software selectable modes of power
reduction — idle mode and power-down
mode. The idle mode freezes the CPU while
allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The
power-down mode saves the RAM and
EEPROM contents but freezes the oscillator,
causing all other chip functions to be
inoperative.
FEATURES
80C51 based architecture
4k × 8 ROM
128 × 8 RAM
Two 16-bit counter/timers
Full duplex serial channel
Boolean processor
Non-volatile 256 × 8-bit EEPROM
(electrically erasable programmable read
only memory)
On-chip voltage multiplier for erase/write
10,000 erase/write cycles per byte
10 years non-volatile data retention
Infinite number of read cycles
User selectable security mode
Block erase capability
Mask-programmable ROM code protection
Memory addressing capability
64k ROM and 64k RAM
Power control modes:
Idle mode
Power-down mode
CMOS and TTL compatible
1.2 to 16MHz or 3.5 to 24MHz
Three package styles
Three temperature ranges
ROM code protection
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
ROMless
Version
ROM Version
NORTH AMERICA PHILIPS
PART ORDER NUMBER
ROMless
Version
ROM Version
TEMPERATURE RANGE °C
AND PACKAGE
FREQ.
(MHz)
P80C851 FBP P83C851 FBP S80C851-4N40 S83C851-4N40 0 to +70, Plastic Dual In-line Package 1.2 to 16
P80C851 IBP P83C851 IBP
0 to +70, Plastic Dual In-line Package 3.5 to 24
P80C851 FBA P83C851 FBA S80C851-4A44 S83C851-4A44 0 to +70, Plastic Leaded Chip Carrier 1.2 to 16
P80C851 IBA P83C851 IBA
0 to +70, Plastic Leaded Chip Carrier 3.5 to 24
P80C851 FBB P83C851 FBB S80C851-4B44 S83C851-4B44
0 to +70, Plastic Quad Flat Pack
1.2 to 16
P80C851 IBB P83C851 IBB
0 to +70, Plastic Quad Flat Pack
3.5 to 24
P80C851 FFP P83C851 FFP S80C851-5N40 S83C851-5N40 –40 to +85, Plastic Dual In-line Package 1.2 to 16
P80C851 FFA P83C851 FFA S80C851-5A44 S83C851-5A44 –40 to +85, Plastic Leaded Chip Carrier 1.2 to 16
P80C851 FFB P83C851 FFB S80C851-5B44 S83C851-5B44
–40 to +85, Plastic Quad Flat Pack
1.2 to 16
P80C851 FHP P83C851 FHP S80C851-6N40 S83C851-6N40 –40 to +125, Plastic Dual In-line Package 1.2 to 16
P80C851 FHA P83C851 FHA S80C851-6A44 S83C851-6A44 –40 to +125, Plastic Leaded Chip Carrier 1.2 to 16
P80C851 FHB P83C851 FHB S80C851-6B44 S83C851-6B44 –40 to +125, Plastic Quad Flat Pack 1.2 to 16
DRAWING
NUMBER
SOT129-1
SOT129-1
SOT187-1
SOT187-1
SOT307-2
SOT307-2
SOT129-1
SOT187-1
SOT307-2
SOT129-1
SOT187-1
SOT307-2
1998 Jul 03
2

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Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
BLOCK DIAGRAM
FREQUENCY
REFERENCE
XTAL2 XTAL1
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(4K x 8 ROM)
DATA
MEMORY
(128 x 8 RAM)
Product specification
80C851/83C851
COUNTERS
T0 T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
EEPROM
(256 x 8)
CPU
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROGRAMMABLE I/O
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
INT0 INT1
EXTERNAL
INTERRUPTS
LOGIC SYMBOL
CONTROL
VDD
XTAL1
VSS
XTAL2
RxD
TxD
INT0
INT1
T0
T1
WR
RD
RST
EA
PSEN
ALE
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SERIAL IN SERIAL OUT
SHARED WITH
PORT 3
ADDRESS AND
DATA BUS
ADDRESS BUS
1998 Jul 03
3