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80C186EA 80C188EA AND 80L186EA 80L188EA
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y 80C186 Upgrade for Power Critical Applications
Y Fully Static Operation
Y True CMOS Inputs and Outputs
Y Integrated Feature Set
Static 186 CPU Core
Power Save Idle and Powerdown
Modes
Clock Generator
2 Independent DMA Channels
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
System-Level Testing Support
(High Impedance Test Mode)
Y Speed Versions Available (5V)
25 MHz (80C186EA25 80C188EA25)
20 MHz (80C186EA20 80C188EA20)
13 MHz (80C186EA13 80C188EA13)
Y Speed Versions Available (3V)
13 MHz (80L186EA13 80L188EA13)
8 MHz (80L186EA8 80L188EA8)
Y Direct Addressing Capability to
1 Mbyte Memory and 64 Kbyte I O
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EA only)
Y Available in the Following Packages
68-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin EIAJ Quad Flat Pack (QFP)
80-Pin Shrink Quad Flat Pack (SQFP)
Y Available in Extended Temperature
Range (b40 C to a85 C)
The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the
features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown
Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor
272432 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272432-003
COPYRIGHT INTEL CORPORATION 1995
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80C186EA 80C188EA 80L186EA 80L188EA
80C186EA 80C188EA AND 80L186EA 80L188EA
16-Bit High Integration Embedded Processor
CONTENTS
PAGE CONTENTS
PAGE
INTRODUCTION
80C186EA CORE ARCHITECTURE
Bus Interface Unit
Clock Generator
80C186EA PERIPHERAL
ARCHITECTURE
Interrupt Control Unit
Timer Counter Unit
DMA Control Unit
Chip-Select Unit
Refresh Control Unit
Power Management
80C187 Interface (80C186EA Only)
ONCE Test Mode
DIFFERENCES BETWEEN THE
80C186XL AND THE 80C186EA
Pinout Compatibility
Operating Modes
TTL vs CMOS Inputs
Timing Specifications
PACKAGE INFORMATION
Prefix Identification
Pin Descriptions
80C186EA Pinout
4 PACKAGE THERMAL
SPECIFICATIONS
4
4 ELECTRICAL SPECIFICATIONS
4 Absolute Maximum Ratings
Recommended Connections
5 DC SPECIFICATIONS
5 ICC versus Frequency and Voltage
5 PDTMR Pin Delay Calculation
7 AC SPECIFICATIONS
7 AC Characteristics 80C186EA20 13
7 AC Characteristics 80L186EA13 8
7 Relative Timings
8
8 AC TEST CONDITIONS
AC TIMING WAVEFORMS
8
DERATING CURVES
8
8 RESET
8 BUS CYCLE WAVEFORMS
8
EXECUTION TIMINGS
9
9 INSTRUCTION SET SUMMARY
9 REVISION HISTORY
15 ERRATA
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25
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36
43
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80C186EA 80C188EA 80L186EA 80L188EA
NOTE
Pin names in parentheses apply to the 80C186EA 80L188EA
Figure 1 80C186EA 80C188EA Block Diagram
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80C186EA 80C188EA 80L186EA 80L188EA
INTRODUCTION
Unless specifically noted all references to the
80C186EA apply to the 80C188EA 80L186EA and
80L188EA References to pins that differ between
the 80C186EA 80L186EA and the 80C188EA
80L188EA are given in parentheses The ‘‘L’’ in the
part number denotes low voltage operation Physi-
cally and functionally the ‘‘C’’ and ‘‘L’’ devices are
identical
The 80C186EA is the second product in a new gen-
eration of low-power high-integration microproces-
sors It enhances the existing 80C186XL family by
offering new features and operating modes The
80C186EA is object code compatible with the
80C186XL embedded processor
The 80L186EA is the 3V version of the 80C186EA
The 80L186EA is functionally identical to the
80C186EA embedded processor Current
80C186EA customers can easily upgrade their de-
signs to use the 80L186EA and benefit from the re-
duced power consumption inherent in 3V operation
The feature set of the 80C186EA 80L186EA meets
the needs of low-power space-critical applications
Low-power applications benefit from the static de-
sign of the CPU core and the integrated peripherals
as well as low voltage operation Minimum current
consumption is achieved by providing a Powerdown
Mode that halts operation of the device and freezes
the clock circuits Peripheral design enhancements
ensure that non-initialized peripherals consume little
current
Space-critical applications benefit from the inte-
gration of commonly used system peripherals Two
flexible DMA channels perform CPU-independent
data transfers A flexible chip select unit simplifies
memory and peripheral interfacing The interrupt unit
provides sources for up to 128 external interrupts
and will prioritize these interrupts with those generat-
ed from the on-chip peripherals Three general pur-
pose timer counters round out the feature set of the
80C186EA
Figure 1 shows a block diagram of the 80C186EA
80C188EA The Execution Unit (EU) is an enhanced
8086 CPU core that includes dedicated hardware to
speed up effective address calculations enhance
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions
string move instructions that operate at full bus
bandwidth ten new instructions and static opera-
tion The Bus Interface Unit (BIU) is the same as that
found on the original 80C186 family products An
independent internal bus is used to allow communi-
cation between the BIU and internal peripherals
80C186EA CORE ARCHITECTURE
Bus Interface Unit
The 80C186EA core incorporates a bus controller
that generates local bus control signals In addition
it employs a HOLD HLDA protocol to share the local
bus with other bus masters
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data off
the local bus during a read operation SRDY and
ARDY input pins are provided to extend a bus cycle
beyond the minimum four states (clocks)
The local bus controller also generates two control
signals (DEN and DT R) when interfacing to exter-
nal transceiver chips This capability allows the addi-
tion of transceivers for simple buffering of the mulit-
plexed address data bus
Clock Generator
The processor provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter and two low-power operating
modes
The oscillator circuit is designed to be used with ei-
ther a parallel resonant fundamental or third-over-
tone mode crystal network Alternatively the oscilla-
tor circuit may be driven from an external clock
source Figure 2 shows the various operating modes
of the oscillator circuit
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components All AC timings are referenced to
CLKOUT
The following parameters are recommended when
choosing a crystal
Temperature Range
Application Specific
ESR (Equivalent Series Resistance)
60X max
C0 (Shunt Capacitance of Crystal)
7 0 pF max
CL (Load Capacitance)
Drive Level
20 pF g 2 pF
2 mW max
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80C186EA 80C188EA 80L186EA 80L188EA
272432 – 4
272432 – 3
(A) Crystal Connection
(B) Clock Connection
NOTE
The L1C1 network is only required when using a third-overtone crystal
Figure 2 Clock Configurations
80C186EA PERIPHERAL
ARCHITECTURE
The 80C186EA has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact yet powerful system The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e g the
interrupt control unit supports interrupt requests
from the timer counters or DMA channels)
The list of integrated peripherals include
 4-Input Interrupt Control Unit
 3-Channel Timer Counter Unit
 2-Channel DMA Unit
 13-Output Chip-Select Unit
 Refresh Control Unit
 Power Management logic
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB) The PCB
can be located in either memory or I O space on
any 256 byte address boundary
Figure 3 provides a list of the registers associated
with the PCB when the processor’s Interrupt Control
Unit is in Master Mode In Slave Mode the defini-
tions of some registers change Figure 4 provides
register definitions specific to Slave Mode
Interrupt Control Unit
The 80C186EA can receive interrupts from a num-
ber of sources both internal and external The Inter-
rupt Control Unit (ICU) serves to merge these re-
quests on a priority basis for individual service by
the CPU Each interrupt source can be independent-
ly masked by the Interrupt Control Unit or all inter-
rupts can be globally masked by the CPU
Internal interrupt sources include the Timers and
DMA channels External interrupt sources come
from the four input pins INT3 0 The NMI interrupt
pin is not controlled by the ICU and is passed direct-
ly to the CPU Although the timers only have one
request input to the ICU separate vector types are
generated to service individual interrupts within the
Timer Unit
Timer Counter Unit
The 80C186EA Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
control or clocking A third timer is not connected to
any external pins and can only be clocked internally
However it can be used to clock the other two timer
channels The TCU can be used to count external
events time external events generate non-repeti-
tive waveforms generate timed interrupts etc
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