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19-0876; Rev 1; 5/96
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________General Description
Maxim’s MX7575/MX7576 are high-speed (5µs/10µs),
microprocessor (µP) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/µs slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
accept input voltages ranging from 0V to 2VREF.
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit µPs through standard CS and RD control sig-
nals. These signals control conversion start and data
access. A BUSY signal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a µP data bus or system l/O port.
Maxim also makes the MAX165, a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the MAX166 is recommended.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
Audio Systems
High-Speed Servo Loops
Low-Power Data Loggers
_________________Pin Configurations
____________________________Features
o Fast Conversion Time: 5µs (MX7575)
10µs (MX7576)
o Built-In Track/Hold Function (MX7575)
o Low Total Unadjusted Error (±1LSB max)
o 50kHz Full-Power Signal Bandwidth (MX7575)
o Single +5V Supply Operation
o 8-Bit µP Interface
o 100ns Data-Access Time
o Low Power: 15mW
o Small-Footprint Packages
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
INL
(LSB)
MX7575JN
0°C to +70°C 18 Plastic DIP ±1
MX7575KN
0°C to +70°C 18 Plastic DIP ±1/2
MX7575JCWN 0°C to +70°C 18 Wide SO
±1
MX7575KCWN 0°C to +70°C 18 Wide SO
±1/2
MX7575JP
0°C to +70°C 20 PLCC
±1
MX7575KP
0°C to +70°C 20 PLCC
±1/2
MX7575J/D
0°C to +70°C Dice*
±1
MX7575AQ
-25°C to +85°C 18 CERDIP**
±1
MX7575BQ
-25°C to +85°C 18 CERDIP**
±1/2
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
** Contact factory for availability.
_______________Functional Diagrams
TOP VIEW
CS 1
RD 2
TP (MODE) 3
BUSY 4
CLK 5
D7 (MSB) 6
D6 7
D5 8
DGND 9
MX7575
MX7576
18 VDD
17 REF
16 AIN
15 AGND
14 D0 (LSB)
13 D1
12 D2
11 D3
10 D4
( ) ARE FOR MX7576 ONLY.
DIP/SO
Pin Configurations continued at end of data sheet.
VDD
18
AIN 16 MX7575
AGND 15
REF 17
CLK 5
CLOCK
OSCILLATOR
TRACK/
HOLD
DAC
SAR
COMP
CS
RD
1
2
TP 3
CONTROL
LOGIC
LATCH AND
THREE-STATE
OUTPUT DRIVERS
4
BUSY
Functional Diagrams continued at end of data sheet.
9
DGND
..6
D7
D0
14
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

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CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND...............................................................-0.3V, +7V
VDD to DGND ..............................................................-0.3V, +7V
AGND to DGND ...............................................-0.3V, VDD + 0.3V
Digital Input Voltage to DGND
(CS, RD, TP, MODE) ......................................-0.3V, VDD + 0.3V
Digital Output Voltage to DGND
(BUSY, D0–D7) ..............................................-0.3V, VDD + 0.3V
CLK Input Voltage to DGND ............................-0.3V, VDD + 0.3V
REF to AGND ...................................................-0.3V, VDD + 0.3V
AIN to AGND....................................................-0.3V, VDD + 0.3V
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ...............889mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
CERDIP (derate 10.53mW/°C above +70°C) .................842mW
PLCC (derate 10.00mW/°C above +70°C) ....................800mW
Operating Temperature Ranges
MX757_J/K ............................................................0°C to +70°C
MX757_A/B ........................................................-25°C to +85°C
MX757_JE/KE ....................................................-40°C to +85°C
MX757_S/T.......................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering,10sec) ..............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V; VREF = 1.23V; AGND = DGND = 0V; fCLK = 4MHz external for MX7575; fCLK = 2MHz external for MX7576;
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ACCURACY
Resolution
8 Bits
Total Unadjusted Error
MX757_K/B/T
TUE
MX757_J/A/S
±1
LSB
±2
Relative Accuracy
MX757_K/B/T
INL
MX757_J/A/S
±1/2
±1
LSB
No-Missing-Codes Resolution
8 Bits
Full-Scale Error
±1 LSB
Full-Scale Tempco
±5 ppm/°C
Offset Error (Note 1)
±1/2 LSB
Offset Tempco
±5 ppm/°C
ANALOG INPUT
Voltage Range
DC Input Impedance
1LSB = 2VREF/256
0
2VREF
V
10 M
Slew Rate, Tracking
MX7575
0.386 V/µs
Signal-to-Noise Ratio (Note 2)
REFERENCE INPUT
SNR MX7575, VIN = 2.46Vp-p at 10kHz, Figure 13
45
dB
Reference Voltage
Reference Current
LOGIC INPUTS CS, RD, MODE
VREF
IREF
±5% variation for specified performance
1.23
500
V
µA
Input Low Voltage
Input High Voltage
Input Current
Input Capacitance (Note 2)
VINL
VINH
IIN
CIN
VIN = 0V or VDD
TA = +25°C
TA = TMIN to TMAX
2.4
0.8 V
V
±1
µA
±10
10 pF
2 _______________________________________________________________________________________

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CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V; VREF = 1.23V; AGND = DGND = 0V; fCLK = 4MHz external for MX7575; fCLK = 2MHz external for MX7576;
TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CLOCK
Input Low Voltage
Input High Voltage
Input Low Current
VINL
VINH
IINL
Input High Current
IINH
LOGIC OUTPUTS (D0–D7, BUSY)
Output Low Voltage
VOL
Output High Voltage
VOH
Floating State Leakage Current
VIN = 0V
VIN = VDD
MX757_J/A/K/B
MX757_S/T
MX757_J/A/K/B
MX757_S/T
ISINK = 1.6mA
ISOURCE = 40µA
VOUT = 0V to VDD, D0–D7
TA = +25°C
TA = TMIN to TMAX
2.4
4.0
0.8 V
V
700
µA
800
700
µA
800
0.4 V
V
±1
µA
±10
Floating State Output
Capacitance (Note 2)
D0–D7
10 pF
CONVERSION TIME (Note 3)
Conversion Time with
External Clock
Conversion Time with
Internal Clock
POWER REQUIREMENTS (Note 4)
Supply Voltage
VDD
Supply Current
IDD
Power Dissipation
Power-Supply Rejection
MX7575: fCLK = 4MHz
MX7576: fCLK = 2MHz
Using recommended
clock components:
RCLK = 100k,
CCLK = 100pF;
TA = +25°C
MX7575
MX7576
±5% for specified performance
MX757_J/A/K/B
MX757_S/T
4.75V < VDD < 5.25V
5
µs
10
5 15
µs
10 30
5V
36
mA
7
15 mW
±1/4 LSB
Note 1: Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Note 2: Sample tested at +25°C to ensure compliance.
Note 3: Accuracy may degrade at conversion times other than those specified.
Note 4: Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575 CS = RD = BUSY = high;
For MX7576 CS = RD = BUSY = MODE = high.
_______________________________________________________________________________________ 3

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CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF = 1.23V, AGND = DGND = 0V.)
PARAMETER
SYMBOL CONDITIONS
CS to RD Setup Time
RD to BUSY Propagation Time
Data-Access Time after RD
RD Pulse Width
CS to RD Hold Time
Data-Access Time after BUSY
Data-Hold Time
BUSY to CS Delay
t1
t2
t3 (Note 6)
t4
t5
t6 (Note 6)
t7 (Note 7)
t8
TA = +25°C
ALL
MIN MAX
0
100
100
100
0
80
10 80
0
TA = TMIN to TMAX
J/K/A/B
S/T
MIN MAX
MIN MAX
00
100 120
100 120
100 120
00
80 100
10 80
10 100
00
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Note 5: Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with
tr = tf = 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
Note 6: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
______________________________________________________________Pin Description
PIN
DIP/SO PLCC
12
23
34
4
5
6
7, 8
9
10–13
14
15
16
17
18
5
6
7
8, 9
10
12–15
16
17
18
19
20
1, 11
NAME
FUNCTION
CS Chip Select Input. CS must be low for the device to be selected or to recognize the RD input.
RD
Read Input. RD must be low to access data. RD is also used to start conversions. See the
Microprocessor Interface section.
TP
(MX7575)
Test Point. Connect to VDD.
MODE Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be
(MX7576) tied high for the synchronous conversion mode and the ROM interface mode.
BUSY
BUSY Output. BUSY going low indicates the start of a conversion. BUSY going high indicates the
end of a conversion.
CLK External Clock Input/Internal Oscillator Pin for frequency setting RC components.
D7 Three-State Data Output, bit 7 (MSB)
D6, D5 Three-State Data Outputs, bits 6 and 5
DGND Digital Ground
D4–D1 Three-State Data Outputs, bits 4–1
D0 Three-State Data Output, bit 0 (LSB)
AGND Analog Ground
AIN Analog Input. 0V to 2VREF input range.
REF Reference Input. +1.23V nominal.
VDD Power-Supply Voltage. +5V nominal.
N.C. No Connect
4 _______________________________________________________________________________________

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CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
D_
3k
100pF
+5V
3k
D_
100pF
D_
3k
+5V
3k
D_
10pF 10pF
DGND
DGND
a) HIGH-Z TO VOH
b) HIGH-Z TO VOL
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 1. Load Circuits for Data-Access Time Test
DGND
DGND
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
_______________Detailed Description
Converter Operation
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see Functional
Diagrams). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see MX7575
Track/Hold and MX7576 Analog Input sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the BUSY sig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
Microprocessor Interface
The CS and RD logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
are performed. In the slow-memory interface mode, CS
and RD are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking CS and RD low,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to VDD to
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from VDD if TP is left open or tied to a voltage other than
VDD.
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking CS and RD
low). The BUSY signal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after RD goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion, BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
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