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9314 DM9314 Quad Latch
General Description
The ’9314 is a multifunctional 4-bit latch designed for gener-
al purpose storage applications in high speed digital sys-
tems All outputs have active pull-up circuitry to provide high
capacitance drive and to provide low impedance in both
logic states for good noise immunity
Connection Diagram
Logic Symbol
Dual-In-Line Package
June 1989
TL F 9788 – 1
Order Number 9314DMQB 9314FMQB or DM9314N
See NS Package Number J16A N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
E
D0 – D3
S0 – S3
MR
Q0 – Q3
Description
Enable Input (Active LOW)
Data Inputs
Set Inputs (Active LOW)
Master Reset Input (Active LOW)
Latch Outputs
TL F 9788 – 2
C1995 National Semiconductor Corporation TL F 9788
RRD-B30M115 Printed in U S A

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Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
Military
b55 C to a125 C
Commercial
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
ts (H)
ts (L)
th (H)
th (L)
ts (H)
th (L)
tw (L)
tw (L)
trec
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
Dn to E
Hold Time HIGH or LOW
Dn to E
Setup Time HIGH Dn to Sn
Hold Time LOW Dn to Sn
E Pulse Width LOW
MR Pulse Width LOW
Recovery Time MR to E
Min
45
2
b55
50
18
0
50
80
80
18
18
0
Military
Nom
5
Max
55
08
b0 8
16
125
Commercial
Min Nom Max
4 75 5
5 25
2
08
b0 8
16
0 70
50
18
0
50
80
80
18
18
0
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
ns
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
VOH
VOL
II
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
VCC e Min II e b 12 mA
VCC e Min IOH e Max
VIL e Max
VCC e Min IOL e Max
VIH e Min
VCC e Min VI e 5 5V
IIH
High Level Input Current
VCC e Max VI e 2 4V
Data Inputs
IIL
Low Level Input Current
VCC e Max VI e 0 4V
Data Inputs
IOS Short Circuit
Output Current
VCC e Max
(Note 2)
MIL
COM
ICC Supply Current
VCC e Max
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time
2
Min
24
b20
b20
Typ
(Note 1)
34
02
Max
b1 5
04
1
40
60
b1 6
b2 7
b70
b70
55
Units
V
V
V
mA
mA
mA
mA
mA

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Switching Characteristics VCC e a5 0V TA e a25 C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
CL e 15 pF
Min Max
Units
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Propagation Delay
E to Qn
Propagation Delay
Dn to Qn
Propagation Delay
MR to Qn
Propagation Delay
Sn to Qn
24
24
ns
12
24 ns
18 ns
24 ns
Functional Description
The ’9314 consists of four latches with a common active
LOW Enable input and active LOW Master Reset input
When the Enable goes HIGH data present in the latches is
stored and the state of the latch is no longer affected by the
Sn and Dn inputs The Master Reset when activated over-
rides all other input conditions forcing all latch outputs LOW
Each of the four latches can be operated in one of two
modes
D-TYPE LATCH For D-type operation the S input of a latch
is held LOW While the common Enable is active the latch
output follows the D input Information present at the latch
output is stored in the latch when the Enable goes HIGH
SET RESET LATCH During set reset operation when the
common Enable is LOW a latch is reset by a LOW on the D
input and can be set by a LOW on the S input if the D input
is HIGH If both S and D inputs are LOW the D input will
dominate and the latch will be reset When the Enable goes
HIGH the latch remains in the last state prior to disable-
ment The two modes of latch operation are shown in the
Truth Table
Truth Table
MR E D S
H LLL
H LHL
H HXX
H LLL
H LHL
H LLH
H LHH
H HXX
L XXX
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Qnb1 e Previous Output State
Qn e Present Output State
Qn
L
H
Qnb1
L
H
L
Qnb1
Qnb1
L
Operation
D Mode
R S Mode
Reset
3