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93AA46/56/66
1K/2K/4K 1.8V Microwire® Serial EEPROM
FEATURES
• Single supply with programming operation down
to 1.8V
• Low power CMOS technology
- 70 µA typical active READ current at 1.8V
- 2 µA typical standby current at 1.8V
• ORG pin selectable memory configuration
- 128 x 8- or 64 x 16-bit organization (93AA46)
- 256 x 8- or 128 x 16-bit organization
(93AA56)
- 512 x 8 or 256 x 16 bit organization (93AA66)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed on
93AA56 and 93AA66
• 1,000,000 E/W cycles guaranteed on 93AA46
• Data retention > 200 years
• 8-pin PDIP/SOIC
(SOIC in JEDEC and EIAJ standards)
• Temperature ranges supported
- Commercial (C):
0°C to +70°C
DESCRIPTION
The Microchip Technology Inc. 93AA46/56/66 are 1K,
2K and 4K low voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or x16
bits depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for low
power non-volatile memory applications. The 93AA
Series is available in standard 8-pin DIP and surface
mount SOIC packages. The rotated pin-out 93AA46X/
56X/66X are offered in the “SN” package only.
PACKAGE TYPES
DIP
CS 1
CLK 2
DI 3
DO 4
SOIC
CS
CLK
DI
DO
SOIC
NU
Vcc
CS
CLK
1
2
3
4
1
2
3
4
8 VCC
7 NU
6 ORG
5 V SS
8 VCC
7 NU
6 ORG
5 V SS
8 ORG
7 Vss
6 DO
5 DI
BLOCK DIAGRAM
VCC
VSS
MEMORY
ARRAY
ADDRESS
DECODER
DI
ORG
CS
CLK
DATA REGISTER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
ADDRESS
COUNTER
OUTPUT
BUFFER
Microwire is a registered trademark of National Semiconductor Incorporated.
DO
© 1996 Microchip Technology Inc.
DS20067G-page 1
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93AA46/56/66
1.0 ELECTRICAL CHARACTERISTICS
TABLE 1-1: PIN FUNCTION TABLE
1.1 Maximum Ratings
VCC ............................................................................ 7.0V
All inputs and outputs w.r.t. VSS.......... -0.6V to VCC +1.0V
Storage temperature................................-65˚C to +150˚C
Ambient temp. with power applied...........-65˚C to +125˚C
Soldering temperature of leads (10 seconds)........+300˚C
ESD protection on all pins ......................................... 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Name
CS
CLK
DI
DO
VSS
ORG
NU
VCC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Not Utilized
Power Supply
TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
VCC = +1.8V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
Min Typ Max Units
Conditions
High level input voltage
VIH1
2.0
— VCC+1
V VCC 2.7V
VIH2 0.7 VCC
VCC+1
V VCC < 2.7V
Low level input voltage
VIL1
-0.3
0.8
V VCC 2.7V
VIL2
-0.3
— 0.2 VCC
V VCC < 2.7V
Low level output voltage
VOL1
0.4
V IOL = 2.1 mA; VCC = 4.5V
VOL2
0.2
V IOL = 100µA; VCC = 1.8V
High level output voltage
VOH1
2.4
V IOH = -400 µA; VCC = 4.5V
VOH2 VCC-0.2
V IOH = -100 µA; VCC = 1.8V
Input leakage current
ILI -10 — 10
µA VIN = 0.1V to VCC
Output leakage current
ILO -10 —
10
µA VOUT = 0.1V to VCC
Pin capacitance
CIN, COUT
7
pF VIN/VOUT = 0V (Note 1 & 2)
(all inputs/outputs)
Tamb = +25˚C, FCLK = 1 MHz
Operating current
ICC write
3
mA FCLK=2 MHz; VCC=5.5V (Note 2)
ICC read
1
mA FCLK = 2 MHz; VCC = 5.5V
500 µA FCLK = 1 MHz; VCC = 3.0V
70 µA FCLK = 1 MHz; VCC = 1.8V
Standby current
ICCS
100 µA CLK = CS = 0V; VCC = 5.5V
30 µA CLK = CS = 0V; VCC = 3.0V
2 µA CLK = CS = 0V; VCC = 1.8V
Clock frequency
FCLK
2 MHz VCC 4.5V
1 MHz VCC < 4.5V
Clock high time
TCKH
250
ns
Clock low time
TCKL
250
ns
Chip select setup time
TCSS
50
ns Relative to CLK
Chip select hold time
TCSH
0
ns Relative to CLK
Chip select low time
TCSL
250
ns
Data input setup time
TDIS
100
ns Relative to CLK
Data input hold time
TDIH
100
ns Relative to CLK
Data output delay time
TPD
400 ns CL = 100 pF
Data output disable time
TCZ
100 ns CL = 100 pF (Note 2)
Status valid time
TSV
500 ns CL = 100 pF
Program cycle time
TWC
4 10 ms ERASE/WRITE mode
TEC 8 15 ms ERAL mode (Vcc = 5V ± 10%)
TWL
16 30
ms WRAL mode (Vcc = 5V ± 10%)
Endurance
93AA46
— 1M — 1M
— 25°C, Vcc = 5.0V, Block Mode
93AA56/66
— 10M — 10M
— (Note 3)
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS20067G-page 2
© 1996 Microchip Technology Inc.

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93AA46/56/66
TABLE 1-3:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-4:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-5:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-6:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-7:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-8:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION)
SB Opcode
1 10
1 00
1 11
1 00
1 01
1 00
1 00
Address
A5 A4 A3 A2 A1 A0
11XXXX
A5 A4 A3 A2 A1 A0
10XXXX
A5 A4 A3 A2 A1 A0
01XXXX
00XXXX
Data In
D15 - D0
D15 - D0
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION)
SB Opcode
1 10
1 00
1 11
1 00
1 01
1 00
1 00
Address
A6 A5 A4 A3 A2 A1 A0
11XXXXX
A6 A5 A4 A3 A2 A1 A0
10XXXXX
A6 A5 A4 A3 A2 A1 A0
01XXXXX
00XXXXX
Data In
D7 - D0
D7 - D0
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION)
SB Opcode
1 10
1 00
1 11
1 00
1 01
1 00
1 00
Address
X A6 A5 A4 A3 A2 A1 A0
11XXXXXX
X A6 A5 A4 A3 A2 A1 A0
10XXXXXX
X A6 A5 A4 A3 A2 A1 A0
01XXXXXX
00XXXXXX
Data In
D15 - D0
D15 - D0
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION)
SB Opcode
1 10
1 00
1 11
1 00
1 01
1 00
1 00
Address
X A7 A6 A5 A4 A3 A2 A1 A0
11XXXXXXX
X A7 A6 A5 A4 A3 A2 A1 A0
10XXXXXXX
X A7 A6 A5 A4 A3 A2 A1 A0
01XXXXXXX
00XXXXXXX
Data In
D7 - D0
D7 - D0
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION)
SB Opcode
1 10
1 00
1 11
1 00
1 01
1 00
1 00
Address
A7 A6 A5 A4 A3 A2 A1 A0
11XXXXXX
A7 A6 A5 A4 A3 A2 A1 A0
10XXXXXX
A7 A6 A5 A4 A3 A2 A1 A0
01XXXXXX
00XXXXXX
Data In
D15 - D0
D15 - D0
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION)
SB Opcode
Address
1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 1 X X X X X X X
1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X X X
1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 00 0 1 X X X X X X X
1 00 0 0 X X X X X X X
Data In
D7 - D0
D7 - D0
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
25
9
9
9
25
25
9
Req. CLK Cycles
18
10
10
10
18
18
10
Req. CLK Cycles
27
11
11
11
27
27
11
Req. CLK Cycles
20
12
12
12
20
20
12
Req. CLK Cycles
27
11
11
11
27
27
11
Req. CLK Cycles
20
12
12
12
20
20
12
© 1996 Microchip Technology Inc.
DS20067G-page 3