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93AA76/86
8K/16K 1.8V Microwire® Serial EEPROM
FEATURES
• Single supply operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 5 µA standby current (typical) at 3.0V
• ORG pin selectable memory configuration
- 1024 x 8 or 512 x 16-bit organization
(93AA76)
- 2048 x 8 or 1024 x 16-bit organization
(93AA86)
• Self-timed ERASE and WRITE cycles
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC package
• Temperature ranges available:
- Commercial (C): 0°C to +70°C
DESCRIPTION
The Microchip Technology Inc. 93AA76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93AA76/86 is available in standard 8-pin DIP and
8-pin surface mount SOIC packages.
PACKAGE TYPES
DIP Package
CS 1
CLK 2
DI 3
DO 4
8 VCC
7 PE
6 ORG
5 VSS
SOIC Package
CS 1
CLK 2
DI 3
DO 4
8 VCC
7 PE
6 ORG
5 VSS
BLOCK DIAGRAM
VCC VSS
Memory
Array
Address
Decoder
Data
Register
DI
Mode
PE
CS
Decode
Logic
CLK
Clock
Generator
Address
Counter
Output
Buffer
DO
Microwire is a registered trademark of National Semiconductor Incorporated.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21130C-page 1

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93AA76/86
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC ..................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to Vcc +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
TABLE 1-1: PIN FUNCTION TABLE
Name
CS
CLK
DI
DO
VSS
ORG
PE
VCC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply
1.2 AC Test Conditions
AC Waveform:
VLO = 2.0V
VHI = Vcc - 0.2V
VHI = 4.0V for
(Note 1)
(Note 2)
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC 4.0V
2: For VCC > 4.0V
TABLE 1-2: DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +1.8V to +6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Parameter
Symbol
Min.
Max.
Units Conditions
High level input voltage VIH1 2.0 VCC +1 V
VIH2
0.7 VCC VCC +1
V
Low level input voltage
VIL1 -0.3 0.8
V
VIL2
-0.3 0.2 VCC
V
Low level output voltage
VOL1
0.4
V
VOL2
0.2 V
High level output voltage
VOH1
2.4
V
VOH2
VCC-0.2
V
Input leakage current
ILI -10 10 µA
Output leakage current ILO -10 10 µA
Pin capacitance
(all inputs/outputs)
CINT
7 pF
Operating current
ICC write
3 mA
ICC read
1 mA
500 µA
Standby current
ICCS — 100 µA
30 µA
Note: This parameter is periodically sampled and not 100% tested.
VCC 2.7V
VCC < 2.7V
VCC 2.7V
VCC < 2.7V
IOL = 2.1 mA; VCC = 4.5V
IOL =100 µA; VCC = VCC Min.
IOH = -400 µA; VCC = 4.5V
IOH = -100 µA; VCC = VCC Min.
VIN = 0.1V to VCC
VOUT = 0.1V to VCC
(Note Note:)
Tamb = +25˚C, FCLK = 1 MHz
VCC = 5.5V
FCLK = 3 MHz; VCC = 5.5V
FCLK = 1 MHz; VCC = 3.0V
CLK = CS = 0V; VCC = 5.5V
CLK = CS = 0V; VCC = 3.0V
DS21130C-page 2
Preliminary
© 1996 Microchip Technology Inc.

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93AA76/86
TABLE 1-3: AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +1.8V to +6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Parameter
Symbol
Min.
Max.
Units Conditions
Clock frequency
FCLK
— 3 MHz 4.5V VCC 6.0V
2 MHz 2.5V VCC 4.5V
1 Mhz 1.8V VCC < 2.5V
Clock high time
TCKH
200 — ns 4.5V VCC 6.0V
300 ns 2.5V VCC < 4.5V
500 ns 1.8V VCC < 2.5V
Clock low time
TCKL
100 — ns 4.5V VCC 6.0V
200 ns 2.5V VCC < 4.5V
500 ns 1.8V VCC < 2.5V
Chip select setup time
TCSS
50 — ns 4.5V VCC 6.0V, Relative to CLK
100 ns 2.5V VCC < 4.5V, Relative to CLK
250 ns 1.8V VCC < 2.5V, Relative to CLK
Chip select hold time
TCSH
0 — ns 1.8V VCC 6.0V
Chip select low time
TCSL
250 — ns 1.8V VCC 6.0V, Relative to CLK
Data input setup time
TDIS
50 — ns 4.5V VCC 6.0V, Relative to CLK
100 ns 2.5V VCC <4.5V, Relative to CLK
250 ns 1.8V VCC < 2.5V, Relative to CLK
Data input hold time
TDIH
50 — ns 4.5V VCC 6.0V, Relative to CLK
100 ns 2.5V VCC < 4.5V, Relative to CLK
250 ns 1.8V VCC < 2.5V, Relative to CLK
Data output delay time
TPD
— 100 ns 4.5V VCC 6.0V, CL = 100 pF
250 ns 2.5V VCC < 4.5V, CL = 100 pF
500 ns 1.8V VCC < 2.5V, CL = 100 pF
Data output disable time TCZ
— 100 ns 4.5V VCC 5.5V (Note 1)
500 ns 1.8V VCC < 4.5V (Note 1)
Status valid time
TSV
— 200 ns 4.5V VCC 6.0V, CL = 100 pF
300 ns 2.5V VCC < 4.5V, CL = 100 pF
500 ns 1.8V VCC < 2.5V, CL = 100 pF
Program cycle time
TWC
— 5 ms ERASE/WRITE mode
TEC — 15 ms ERAL mode
TWL — 30 ms WRAL mode
Endurance
10M
— cycles 25°C, VCC = 5.0V, Block Mode
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
© 1996 Microchip Technology Inc.
Preliminary
DS21130C-page 3

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93AA76/86
TABLE 1-4: INSTRUCTION SET FOR 93AA76: ORG=1 (X16 ORGANIZATION)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-5:
SB Opcode
Address
Data In Data Out
1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0
— D15 - D0
1 00 1 1 X X X X X X X X
— High-Z
1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0
— (RDY/BSY)
1 00 1 0 X X X X X X X X
— (RDY/BSY)
1
01 X A8 A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0 (RDY/BSY)
1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY)
1 00 0 0 X X X X X X X X
— High-Z
INSTRUCTION SET FOR 93AA76: ORG=0 (X8 ORGANIZATION)
Req. CLK Cycles
29
13
13
13
29
29
13
Instruction SB Opcode
Address
Data In Data Out
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-6:
1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
— D7 - D0
1 00 1 1 X X X X X X X X
— High-Z
1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
— (RDY/BSY)
1 00 1 0 X X X X X X X X
— (RDY/BSY)
1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)
1 00 0 1 X X X X X X X X
D7 - D0 (RDY/BSY)
1 00 0 0 X X X X X X X X
— High-Z
INSTRUCTION SET FOR 93AA86: ORG=1 (X16 ORGANIZATION)
Req. CLK
Cycles
22
14
14
14
22
22
14
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-7:
SB Opcode
Address
Data In Data Out
1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
— D15 - D0
1 00 1 1 X X X X X X X X
— High-Z
1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
— (RDY/BSY)
1 00 1 0 X X X X X X X X
— (RDY/BSY)
1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)
1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY)
1 00 0 0 X X X X X X X X
— High-Z
INSTRUCTION SET FOR 93AA86: ORG=0 (X8 ORGANIZATION)
Req. CLK Cycles
29
13
13
13
29
29
13
Instruction SB Opcode
Address
Data In Data Out Req. CLK Cycles
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
1
10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
— D7 - D0
1 00 1 1 X X X X X X X X — High-Z
1
11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
— (RDY/BSY)
1 00 1 0 X X X X X X X X — (RDY/BSY)
1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)
1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY)
1 00 0 0 X X X X X X X X — High-Z
22
14
14
14
22
22
14
DS21130C-page 4
Preliminary
© 1996 Microchip Technology Inc.

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2.0 PRINCIPLES OF OPERATION
When the ORG pin is connected to VCC, the x16 orga-
nization is selected. When it is connected to ground, the
x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the READY/BUSY status dur-
ing a programming operation. The READY/BUSY sta-
tus can be verified during an Erase/Write operation by
polling the DO pin; DO low indicates that programming
is still in progress, while DO high indicates the device is
ready. The DO will enter the high impedance state on
the falling edge of the CS.
2.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0, the
higher the voltage at the Data Out pin.
93AA76/86
2.3 Erase/Write Enable and Disable
(EWEN, EWDS)
The 93AA76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should fol-
low all programming operations. Execution of a READ
instruction is independent of both the EWEN and
EWDS instructions.
2.4 Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
© 1996 Microchip Technology Inc.
Preliminary
DS21130C-page 5