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93C06/46
256 Bit/1K 5.0V CMOS Serial EEPROM
FEATURES
• Low power CMOS technology
• 16 bit memory organization
- 6 x 16 bit organization (93C06)
- 64 x 16 bit organization (93C46)
• Single 5 volt only operation
• Self-timed ERASE and WRITE cycles
• Automatic ERASE before WRITE
• Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data Retention > 200 years
• 8-pin DIP or SOIC package
• Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
- Automotive: -40˚C to +125˚C
• 2 ms program cycle time
DESCRIPTION
The Microchip Technology Inc. 93C06/46 family of
Serial Electrically Erasable PROMs are configured in a
x16 organization. Advanced CMOS technology makes
these devices ideal for low-power non-volatile memory
applications. The 93C06/46 is available in the standard
8-pin DIP and surface mount SOIC packages. The
93C46X comes as SOIC only.
These devices offer fast (1 ms) byte write and extended
(-40˚C to +125˚C) temperature operation. It is recom-
mended that all other applications use Microchip’s
93LC46.
PACKAGE TYPE
DIP
CS 1
8 VCC
CLK 2 93C06 7 NC
93C46
DI 3
6 NC
DO 4
5 VSS
SOIC
CS
CLK
DI
DO
18
27
93C06
3 93C46 6
45
VCC
NC
NC
VSS
NC
VCC
CS
CLK
18
27
93C46X
36
45
NC
VSS
DO
DI
BLOCK DIAGRAM
VCC
VSS
MEMORY
ARRAY
ADDRESS
DECODER
DATA REGISTER
DI
MODE
DECODE
CS LOGIC
CLOCK
CLK
GENERATOR
OUTPUT
BUFFER
DO
© 1995 Microchip Technology Inc.
DS11179C-page 1

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93C06/46
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC ............................................................................ 7.0V
All inputs and outputs w.r.t. VSS......... -0.6V to VCC +1.0V
Storage temperature................................-65˚C to +150˚C
Ambient temperature with power applied . -65˚C to +125C
Soldering temperature of leads (10 seconds)........+300˚C
ESD protection on all pins ......................................... 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
Name
CS
CLK
DI
DO
VSS
NC
VCC
PIN FUNCTION TABLE
Function
Chip Select
Serial Clock
Data In
Data Out
Ground
No Connect; No Internal
Connection
+5V Power Supply
TABLE 1-2: DC CHARACTERISTICS
VCC = +5V (±10%)
Commercial:
Industrial:
Automotive:
Tamb = 0˚C to +70˚C
Tamb = -40˚C to +85˚C
Tamb = -40˚C to +125˚C (Note 3)
Parameter
Symbol
Min Max Units
Conditions
VCC detector threshold
VTH
2.8 4.5
V
High level input voltage
VIH 2.0 VCC + 1 V
Low level input voltage
VIL
-0.3 0.8
V
High level output voltage
VOH
2.4 —
V IOH = -400 µA
Low level output voltage
VOL — 0.4 V IOL = 3.2 mA
Input leakage current
ILI — 10 µA VIN = 0V to VCC (Note 1)
Output leakage current
ILO — 10 µA VOUT = 0V to VCC (Note 1)
Pin capacitance
(all inputs/outputs)
CIN, COUT
7
pF VIN/VOUT = 0V (Note 2)
Tamb = +25˚C, f = 1 MHz
Operating current (all modes)
ICC write
4 mA FCLK = 1 MHz, VCC = 5.5V
Standby current
ICCS
— 100 µA CS = 0V, VCC = 5.5V
Note 1: Internal resistor pull-up at Pin 6.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: For operation above 85˚C, endurance is rated at 10,000 ERASE/WRITE cycles.
FIGURE 1-1: SYNCHRONOUS DATA TIMING
TCKH
TCKL
TCSH
CLK
TDIS
DI
VALID
CS TCSS
TDIH
TDIS
TDIH
VALID
TCSL
TPD TPD TCZ
HIGH
DO
VALID
VALID
Z
DS11179C-page 2
© 1995 Microchip Technology Inc.

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93C06/46
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
Clock frequency
Clock high time
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time (from CS = low)
Data output disable time (from last clock)
Status valid time
Program cycle time (Auto Erase and Write)
FCLK
TCKH
TCKL
TCSS
TCSH
TCSL
TDIS
TDIH
TPD
TCZ
TDDZ
TSV
TWC
Min
500
500
50
0
100
100
100
0
0
Erase cycle time
TEC
Max
1
400
100
400
100
2
15
1
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
Conditions
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
For ERAL and WRAL
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a programming cycle which is already initiated
and/or in progress will be completed, regardless of the
CS input signal. If CS is brought LOW during a pro-
gram cycle, the device will go into standby mode as
soon as the programming cycle is completed.
CS must be LOW for 100 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C06/46.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime (with respect to clock HIGH time (TCKH)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status. (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition, the specified num-
ber of clock cycles (respectively LOW to HIGH transi-
tions of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become “Don't
Care” inputs waiting for a new start condition to be
detected.
Note: CS must go LOW between consecutive
instructions.
2.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the CLK input (TPD after the posi-
tive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (TCSL) from the falling edge of the CLK which
clocked in the last DI bit (D0 for WRITE, A0 for ERASE)
and an ERASE or WRITE operation has been initiated.
© 1995 Microchip Technology Inc.
DS11179C-page 3

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93C06/46
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
DI and DO can be connected together to perform a 3-
wire interface (CS, CLK, DI/DO).
Care must be taken with the leading dummy zero which
is outputted after a READ command has been
detected. Also, the controlling device must not drive
the DI/DO bus during Erase and Write cycles if the
READY/BUSY status information is outputted by the
93C06/46.
INSTRUCTION SET - 93C06
Instruction Start BIT
Opcode
OP1 OP2
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAL
1 10
1 01
1 11
1 00
1 00
1 00
1 00
INSTRUCTION SET - 93C46
Instruction
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAL
Start BIT
1
1
1
1
1
1
1
Opcode
OP1 OP2
10
01
11
00
00
00
00
Address
0 0 A3 A2 A1 A0
0 0 A3 A2 A1 A0
0 0 A3 A2 A1 A0
11 X X X X
00 X X X X
10 X X X X
01 X X X X
Address
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
11XXXX
00XXXX
10XXXX
01XXXX
Number of
Data In
D15 - D0
D15 - D0
Number of
Data In
D15 - D0
D15 - D0
Data Out
D15 - D0
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
(RDY/BSY)
(RDY/BSY)
Data Out
D15 - D0
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
(RDY/BSY)
(RDY/BSY)
Req. CLK
Cycles
25
25
9
9
9
9
25
Req. CLK
Cycles
25
25
9
9
9
9
25
3.0 FUNCTIONAL DESCRIPTION
3.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
3.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
3.3 Data Protection
During power-up, all modes of operation are inhibited
until VCC has reached 2.8V. During power-down, the
source data protection circuitry acts to inhibit all modes
when VCC has fallen below 2.8V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed. After programming is completed, the
EWDS instruction offers added protection against unin-
tended data changes.
DS11179C-page 4
© 1995 Microchip Technology Inc.

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93C06/46
3.4 READ Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
bit (logical 0) precedes the 16-bit output string. The
output data changes during the HIGH state of the sys-
tem clock (CLK). The dummy bit is output TPD after
the positive edge of CLK, which was used to clock in
the last address bit (A0). Therefore, care must be
taken if DI and DO are connected together as a bus
contention will occur for one clock cycle if A0 has been
a one.
DO will go into HIGH-Z mode with the positive edge of
the next CLK cycle. This follows the output of the last
data bit D0 or the low going edge of CS, which ever
occurs first.
DO remains stable between CLK cycles for an unlim-
ited time as long as CS stays HIGH.
The most significant data bit (D15) is always output
first, followed by the lower significant bits (D14 - D0).
FIGURE 3-1: READ MODE
CLK
3.5 WRITE Mode
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. The most
significant data bit (D15) has to be clocked in first, fol-
lowed by the lower significant data bits (D14 – D0). If
a WRITE instruction is recognized by the device and all
data bits have been clocked in, the device performs an
automatic ERASE cycle on the specified address
before the data are written. The WRITE cycle is com-
pletely self-timed and commences automatically after
the rising edge of the CLK for the last data bit (D0).
The WRITE cycle takes 2 ms maximum.
T CSL
CS
SB OP1 OP2 A5 A4 A3
A0
DI
11 0
T PD
T DDZ
DO
HIGH - Z
0 D15
D0
FIGURE 3-2: WRITE MODE
CLK
CS
SB OP1 OP2 A5 A4 A3
A0 D15
DI
10 1
DO HIGH - Z
NEW INSTRUCTION
OR STANDBY (CS = 0)
TCSL
TCSL
STATUS
CHECK
D0
TSV
BSY RDY
TWC
NEW INSTRUCTION
OR STANDBY (CS = 0)
TDDZ
© 1995 Microchip Technology Inc.
DS11179C-page 5